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Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
llvm-svn: 118152
This commit is contained in:
Evan Cheng
parent
3894287c96
commit
b41703bc2f
@ -598,6 +598,11 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
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// ARM v5TE+ and Thumb2 has preload instructions.
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if (Subtarget->isThumb2() ||
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(!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps()))
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setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
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// Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
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if (!Subtarget->hasV6Ops()) {
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
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@ -991,17 +991,18 @@ def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
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//
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// A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
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// The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
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multiclass APreLoad<bit data, bit read, string opc> {
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multiclass APreLoad<bits<2> data_read, string opc> {
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def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, NoItinerary,
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!strconcat(opc, "\t$addr"), []> {
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!strconcat(opc, "\t$addr"),
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[(prefetch addrmode_imm12:$addr, imm, (i32 data_read))]> {
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bits<4> Rt;
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bits<17> addr;
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let Inst{31-26} = 0b111101;
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let Inst{25} = 0; // 0 for immediate form
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let Inst{24} = data;
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let Inst{24} = data_read{1};
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let Inst{23} = addr{12}; // U (add = ('U' == 1))
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let Inst{22} = read;
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let Inst{22} = data_read{0};
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let Inst{21-20} = 0b01;
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let Inst{19-16} = addr{16-13}; // Rn
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let Inst{15-12} = Rt;
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@ -1009,23 +1010,24 @@ multiclass APreLoad<bit data, bit read, string opc> {
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}
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def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, NoItinerary,
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!strconcat(opc, "\t$shift"), []> {
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!strconcat(opc, "\t$shift"),
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[(prefetch ldst_so_reg:$shift, imm, (i32 data_read))]> {
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bits<4> Rt;
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bits<17> shift;
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let Inst{31-26} = 0b111101;
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let Inst{25} = 1; // 1 for register form
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let Inst{24} = data;
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let Inst{24} = data_read{1};
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let Inst{23} = shift{12}; // U (add = ('U' == 1))
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let Inst{22} = read;
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let Inst{22} = data_read{0};
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let Inst{21-20} = 0b01;
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let Inst{19-16} = shift{16-13}; // Rn
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let Inst{11-0} = shift{11-0};
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}
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}
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defm PLD : APreLoad<1, 1, "pld">;
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defm PLDW : APreLoad<1, 0, "pldw">;
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defm PLI : APreLoad<0, 1, "pli">;
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defm PLD : APreLoad<3, "pld">;
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defm PLDW : APreLoad<2, "pldw">;
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defm PLI : APreLoad<1, "pli">;
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def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
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"setend\t$end",
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@ -610,6 +610,8 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
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let Inst{20} = 1; // load
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let Inst{11-6} = 0b000000;
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}
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// FIXME: Is the pci variant actually needed?
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def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), iii,
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opc, ".w\t$dst, $addr",
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[(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
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@ -1172,10 +1174,11 @@ def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
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//
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// A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
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// The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
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multiclass T2Ipl<bit instr, bit write, string opc> {
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multiclass T2Ipl<bit instr, bit write, bits<2> data_read, string opc> {
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def i12 : T2I<(outs), (ins GPR:$base, i32imm:$imm), IIC_iLoad_i, opc,
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"\t[$base, $imm]", []> {
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def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_iLoad_i, opc,
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"\t$addr",
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[(prefetch t2addrmode_imm12:$addr, imm, (i32 data_read))]> {
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let Inst{31-25} = 0b1111100;
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let Inst{24} = instr;
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let Inst{23} = 1; // U = 1
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@ -1185,8 +1188,9 @@ multiclass T2Ipl<bit instr, bit write, string opc> {
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let Inst{15-12} = 0b1111;
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}
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def i8 : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoad_i, opc,
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"\t[$base, $imm]", []> {
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def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_iLoad_i, opc,
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"\t$addr",
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[(prefetch t2addrmode_imm8:$addr, imm, (i32 data_read))]> {
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let Inst{31-25} = 0b1111100;
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let Inst{24} = instr;
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let Inst{23} = 0; // U = 0
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@ -1197,9 +1201,23 @@ multiclass T2Ipl<bit instr, bit write, string opc> {
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let Inst{11-8} = 0b1100;
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}
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let isCodeGenOnly = 1 in // $base doesn't exist in asmstring?
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def pci : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoad_i, opc,
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"\t[pc, $imm]", []> {
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def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_iLoad_i, opc,
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"\t$addr",
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[(prefetch t2addrmode_so_reg:$addr, imm, (i32 data_read))]> {
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let Inst{31-25} = 0b1111100;
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let Inst{24} = instr;
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let Inst{23} = 0; // add = TRUE for T1
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let Inst{22} = 0;
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let Inst{21} = write;
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let Inst{20} = 1;
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let Inst{15-12} = 0b1111;
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let Inst{11-6} = 0000000;
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}
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let isCodeGenOnly = 1 in
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def pci : T2Ipc<(outs), (ins i32imm:$addr), IIC_iLoad_i, opc,
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"\t$addr",
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[]> {
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let Inst{31-25} = 0b1111100;
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let Inst{24} = instr;
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let Inst{23} = ?; // add = (U == 1)
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@ -1209,36 +1227,11 @@ multiclass T2Ipl<bit instr, bit write, string opc> {
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let Inst{19-16} = 0b1111; // Rn = 0b1111
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let Inst{15-12} = 0b1111;
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}
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def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoad_i, opc,
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"\t[$base, $a]", []> {
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let Inst{31-25} = 0b1111100;
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let Inst{24} = instr;
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let Inst{23} = 0; // add = TRUE for T1
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let Inst{22} = 0;
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let Inst{21} = write;
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let Inst{20} = 1;
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let Inst{15-12} = 0b1111;
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let Inst{11-6} = 0000000;
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let Inst{5-4} = 0b00; // no shift is applied
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}
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def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoad_i, opc,
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"\t[$base, $a, lsl $shamt]", []> {
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let Inst{31-25} = 0b1111100;
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let Inst{24} = instr;
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let Inst{23} = 0; // add = TRUE for T1
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let Inst{22} = 0;
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let Inst{21} = write;
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let Inst{20} = 1;
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let Inst{15-12} = 0b1111;
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let Inst{11-6} = 0000000;
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}
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}
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defm t2PLD : T2Ipl<0, 0, "pld">;
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defm t2PLDW : T2Ipl<0, 1, "pldw">;
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defm t2PLI : T2Ipl<1, 0, "pli">;
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defm t2PLD : T2Ipl<0, 0, 3, "pld">;
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defm t2PLDW : T2Ipl<0, 1, 2, "pldw">;
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defm t2PLI : T2Ipl<1, 0, 1, "pli">;
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//===----------------------------------------------------------------------===//
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// Load / store multiple Instructions.
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@ -355,11 +355,11 @@ static inline bool Thumb2PreloadOpcodeNoPCI(unsigned Opcode) {
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default:
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return false;
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case ARM::t2PLDi12: case ARM::t2PLDi8:
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case ARM::t2PLDr: case ARM::t2PLDs:
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case ARM::t2PLDs:
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case ARM::t2PLDWi12: case ARM::t2PLDWi8:
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case ARM::t2PLDWr: case ARM::t2PLDWs:
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case ARM::t2PLDWs:
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case ARM::t2PLIi12: case ARM::t2PLIi8:
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case ARM::t2PLIr: case ARM::t2PLIs:
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case ARM::t2PLIs:
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return true;
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}
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}
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@ -369,13 +369,13 @@ static inline unsigned T2Morph2Preload2PCI(unsigned Opcode) {
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default:
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return 0;
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case ARM::t2PLDi12: case ARM::t2PLDi8:
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case ARM::t2PLDr: case ARM::t2PLDs:
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case ARM::t2PLDs:
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return ARM::t2PLDpci;
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case ARM::t2PLDWi12: case ARM::t2PLDWi8:
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case ARM::t2PLDWr: case ARM::t2PLDWs:
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case ARM::t2PLDWs:
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return ARM::t2PLDWpci;
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case ARM::t2PLIi12: case ARM::t2PLIi8:
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case ARM::t2PLIr: case ARM::t2PLIs:
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case ARM::t2PLIs:
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return ARM::t2PLIpci;
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}
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}
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@ -1731,11 +1731,11 @@ static inline bool Thumb2PreloadOpcode(unsigned Opcode) {
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default:
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return false;
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case ARM::t2PLDi12: case ARM::t2PLDi8: case ARM::t2PLDpci:
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case ARM::t2PLDr: case ARM::t2PLDs:
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case ARM::t2PLDs:
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case ARM::t2PLDWi12: case ARM::t2PLDWi8: case ARM::t2PLDWpci:
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case ARM::t2PLDWr: case ARM::t2PLDWs:
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case ARM::t2PLDWs:
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case ARM::t2PLIi12: case ARM::t2PLIi8: case ARM::t2PLIpci:
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case ARM::t2PLIr: case ARM::t2PLIs:
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case ARM::t2PLIs:
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return true;
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}
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}
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64
test/CodeGen/ARM/prefetch.ll
Normal file
64
test/CodeGen/ARM/prefetch.ll
Normal file
@ -0,0 +1,64 @@
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; RUN: llc < %s -march=thumb -mattr=-thumb2 | not grep pld
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; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s -check-prefix=THUMB2
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; RUN: llc < %s -march=arm -mattr=+v5te | FileCheck %s -check-prefix=ARM
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; rdar://8601536
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define void @t1(i8* %ptr) nounwind {
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entry:
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; ARM: t1:
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; ARM: pli [r0]
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; ARM: pldw [r0]
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; ARM: pld [r0]
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; THUMB2: t1:
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; THUMB2: pli [r0]
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; THUMB2: pldw [r0]
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; THUMB2: pld [r0]
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 )
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ret void
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}
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define void @t2(i8* %ptr) nounwind {
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entry:
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; ARM: t2:
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; ARM: pld [r0, #1023]
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; THUMB2: t2:
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; THUMB2: pld [r0, #1023]
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%tmp = getelementptr i8* %ptr, i32 1023
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tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3 )
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ret void
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}
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define void @t3(i32 %base, i32 %offset) nounwind {
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entry:
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; ARM: t3:
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; ARM: pld [r0, r1, lsr #2]
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; THUMB2: t3:
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; THUMB2: lsrs r1, r1, #2
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; THUMB2: pld [r0, r1]
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%tmp1 = lshr i32 %offset, 2
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%tmp2 = add i32 %base, %tmp1
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%tmp3 = inttoptr i32 %tmp2 to i8*
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tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 )
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ret void
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}
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define void @t4(i32 %base, i32 %offset) nounwind {
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entry:
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; ARM: t4:
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; ARM: pld [r0, r1, lsl #2]
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; THUMB2: t4:
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; THUMB2: pld [r0, r1, lsl #2]
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%tmp1 = shl i32 %offset, 2
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%tmp2 = add i32 %base, %tmp1
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%tmp3 = inttoptr i32 %tmp2 to i8*
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tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 )
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ret void
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}
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declare void @llvm.prefetch(i8*, i32, i32) nounwind
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