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R600/SI: Add support for v4i32 and v4f32 kernel args
Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 184820
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@ -38,10 +38,11 @@ def CC_SI : CallingConv<[
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// Calling convention for SI compute kernels
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def CC_SI_Kernel : CallingConv<[
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CCIfType<[i64], CCAssignToStack <8, 4>>,
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CCIfType<[i32, f32], CCAssignToStack <4, 4>>,
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CCIfType<[i16], CCAssignToStack <2, 4>>,
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CCIfType<[i8], CCAssignToStack <1, 4>>
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CCIfType<[v4i32, v4f32], CCAssignToStack <16, 4>>,
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CCIfType<[i64], CCAssignToStack < 8, 4>>,
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CCIfType<[i32, f32], CCAssignToStack < 4, 4>>,
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CCIfType<[i16], CCAssignToStack < 2, 4>>,
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CCIfType<[i8], CCAssignToStack < 1, 4>>
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]>;
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def CC_AMDGPU : CallingConv<[
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@ -1,16 +1,20 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; CHECK: @v4i32_kernel_arg
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; CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 40
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
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; R600-CHECK: @v4i32_kernel_arg
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; R600-CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 40
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; SI-CHECK: @v4i32_kernel_arg
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; SI-CHECK: BUFFER_STORE_DWORDX4
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define void @v4i32_kernel_arg(<4 x i32> addrspace(1)* %out, <4 x i32> %in) {
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entry:
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store <4 x i32> %in, <4 x i32> addrspace(1)* %out
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ret void
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}
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; CHECK: @v4f32_kernel_arg
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; CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 40
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; R600-CHECK: @v4f32_kernel_arg
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; R600-CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 40
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; SI-CHECK: @v4f32_kernel_arg
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; SI-CHECK: BUFFER_STORE_DWORDX4
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define void @v4f32_kernel_args(<4 x float> addrspace(1)* %out, <4 x float> %in) {
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entry:
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store <4 x float> %in, <4 x float> addrspace(1)* %out
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