RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-08 20:30:50 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[Hexagon] Adding logical-logical accumulation instructions and tests.

Browse Source 
llvm-svn: 224288
This commit is contained in:
Colin LeMahieu 2014-12-15 23:19:07 +00:00
parent 0cdde3ea1f
commit b56764d577
2 changed files with 52 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

59
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -2178,9 +2178,49 @@ let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in {
IntRegs:$src1))]>, ImmRegRel;
}
let CextOpcode = "ADD_acc", isCodeGenOnly = 0 in {
let isExtentSigned = 1 in
def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext,
[(set (i32 IntRegs:$dst),
(add (add (i32 IntRegs:$src2), s8_16ExtPred:$src3),
(i32 IntRegs:$src1)))]>, ImmRegRel;
def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0,
[(set (i32 IntRegs:$dst),
(add (add (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
(i32 IntRegs:$src1)))]>, ImmRegRel;
}
let CextOpcode = "SUB_acc", isCodeGenOnly = 0 in {
let isExtentSigned = 1 in
def M2_naccii : T_MType_acc_ri <"-= add", 0b101, s8Ext>, ImmRegRel;
def M2_nacci : T_MType_acc_rr <"-= add", 0b100, 0b001, 0>, ImmRegRel;
}
let Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in
def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8Ext>;
let isCodeGenOnly = 0 in {
def M2_xor_xacc : T_MType_acc_rr < "^= xor", 0b100, 0b011, 0>;
def M2_subacc : T_MType_acc_rr <"+= sub", 0b000, 0b011, 1>;
}
class T_MType_acc_pat1 <InstHexagon MI, SDNode firstOp, SDNode secOp,
PatLeaf ImmPred>
: Pat <(secOp IntRegs:$src1, (firstOp IntRegs:$src2, ImmPred:$src3)),
(MI IntRegs:$src1, IntRegs:$src2, ImmPred:$src3)>;
class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp>
: Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2, IntRegs:$src3))),
(MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>;
def : T_MType_acc_pat1 <M2_macsin, mul, sub, u8ExtPred>;
def : T_MType_acc_pat1 <M2_naccii, add, sub, s8_16ExtPred>;
def : T_MType_acc_pat2 <M2_nacci, add, sub>;
// Multiply and use lower result.
// Rd=+mpyi(Rs,#u8)
let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
@ -2307,16 +2347,6 @@ def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
(i64 (anyext (i32 IntRegs:$src3))))))],
"$src1 = $dst">;
let InputType = "reg", CextOpcode = "ADD_acc" in
def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
IntRegs:$src2, IntRegs:$src3),
"$dst += add($src2, $src3)",
[(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
(i32 IntRegs:$src3)),
(i32 IntRegs:$src1)))],
"$src1 = $dst">, ImmRegRel;
let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
InputType = "imm", CextOpcode = "ADD_acc" in
def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
@ -2327,15 +2357,6 @@ def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
(i32 IntRegs:$src1)))],
"$src1 = $dst">, ImmRegRel;
let CextOpcode = "SUB_acc", InputType = "reg" in
def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
IntRegs:$src2, IntRegs:$src3),
"$dst -= add($src2, $src3)",
[(set (i32 IntRegs:$dst),
(sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
(i32 IntRegs:$src3))))],
"$src1 = $dst">, ImmRegRel;
let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
CextOpcode = "SUB_acc", InputType = "imm" in
def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,

12
test/MC/Disassembler/Hexagon/xtype_alu.txt
View File

@ -1,5 +1,13 @@
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
0xf1 0xc2 0x15 0xe2
# CHECK: r17 += add(r21, #23)
0xf1 0xc2 0x95 0xe2
# CHECK: r17 -= add(r21, #23)
0x31 0xdf 0x15 0xef
# CHECK: r17 += add(r21, r31)
0x31 0xdf 0x95 0xef
# CHECK: r17 -= add(r21, r31)
0xf0 0xde 0x14 0xd3
# CHECK: r17:16 = add(r21:20, r31:30)
0x11 0xd5 0x1f 0xd5
@ -36,6 +44,8 @@
# CHECK: r17:16 = add(r21:20, r31:30):raw:hi
0x10 0xde 0xf4 0xd3
# CHECK: r17:16 = and(r21:20, r31:30)
0x71 0xdf 0x95 0xef
# CHECK: r17 ^= xor(r21, r31)
0x11 0xdf 0xd5 0xd5
# CHECK: r17 = max(r21, r31)
0x91 0xdf 0xd5 0xd5
@ -54,6 +64,8 @@
# CHECK: r17:16 = minu(r21:20, r31:30)
0x50 0xde 0xf4 0xd3
# CHECK: r17:16 = or(r21:20, r31:30)
0x71 0xd5 0x1f 0xef
# CHECK: r17 += sub(r21, r31)
0x11 0xd5 0x3f 0xd5
# CHECK: r17 = sub(r21.l, r31.l)
0x51 0xd5 0x3f 0xd5