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More ARM encoding bits. LDRH now encodes properly.

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llvm-svn: 119529
This commit is contained in:
Jim Grosbach 2010-11-17 18:11:11 +00:00
parent 878ec25f02
commit b640b6a7b4
2 changed files with 47 additions and 30 deletions
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59
lib/Target/ARM/ARMInstrFormats.td
View File

@ -505,26 +505,37 @@ class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
opc, asm, "", pattern> {
let Inst{4} = 1;
let Inst{5} = 1; // H bit
let Inst{6} = 0; // S bit
let Inst{7} = 1;
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
bits<14> addr;
bits<4> Rt;
let Inst{27-25} = 0b000;
let Inst{24} = 1; // P bit
let Inst{23} = addr{8}; // U bit
let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
let Inst{21} = 0; // W bit
let Inst{20} = 1; // L bit
let Inst{19-16} = addr{12-9}; // Rn
let Inst{15-12} = Rt; // Rt
let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{7-4} = 0b1011;
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
}
class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
string asm, list<dag> pattern>
: XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
asm, "", pattern> {
let Inst{4} = 1;
let Inst{5} = 1; // H bit
let Inst{6} = 0; // S bit
let Inst{7} = 1;
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
bits<14> addr;
bits<4> Rt;
let Inst{27-25} = 0b000;
let Inst{24} = 1; // P bit
let Inst{23} = addr{8}; // U bit
let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
let Inst{21} = 0; // W bit
let Inst{20} = 1; // L bit
let Inst{19-16} = addr{12-9}; // Rn
let Inst{15-12} = Rt; // Rt
let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{7-4} = 0b1011;
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
}
class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
@ -548,13 +559,19 @@ class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
string asm, list<dag> pattern>
: XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
asm, "", pattern> {
let Inst{4} = 1;
let Inst{5} = 1; // H bit
let Inst{6} = 1; // S bit
let Inst{7} = 1;
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
bits<14> addr;
bits<4> Rt;
let Inst{27-25} = 0b000;
let Inst{24} = 1; // P bit
let Inst{23} = addr{8}; // U bit
let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
let Inst{21} = 0; // W bit
let Inst{20} = 1; // L bit
let Inst{19-16} = addr{12-9}; // Rn
let Inst{15-12} = Rt; // Rt
let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{7-4} = 0b1111;
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
}
class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, list<dag> pattern>

18
lib/Target/ARM/ARMInstrInfo.td
View File

@ -1538,18 +1538,18 @@ def LDRcp : AIldst1<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
}
// Loads with zero extension
def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
IIC_iLoad_bh_r, "ldrh", "\t$dst, $addr",
[(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
def LDRH : AI3ldh<(outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
[(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
// Loads with sign extension
def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
IIC_iLoad_bh_r, "ldrsh", "\t$dst, $addr",
[(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
def LDRSH : AI3ldsh<(outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
[(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
IIC_iLoad_bh_r, "ldrsb", "\t$dst, $addr",
[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
def LDRSB : AI3ldsb<(outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
[(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?