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[ARM] FP16 vmaxnm/vminnm scalar instructions
This adds code generation support for the FP16 vmaxnm/vminnm scalar instructions. Differential Revision: https://reviews.llvm.org/D44675 llvm-svn: 330034
This commit is contained in:
Sjoerd Meijer
parent
f975577120
commit
b69b9d3362
@ -527,6 +527,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::BITCAST, MVT::i16, Custom);
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setOperationAction(ISD::BITCAST, MVT::i32, Custom);
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setOperationAction(ISD::BITCAST, MVT::f16, Custom);
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setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
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setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
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}
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for (MVT VT : MVT::vector_valuetypes()) {
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@ -1147,6 +1150,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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if (Subtarget->hasNEON()) {
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// vmin and vmax aren't available in a scalar form, so we use
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// a NEON instruction with an undef lane instead.
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setOperationAction(ISD::FMINNAN, MVT::f16, Legal);
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setOperationAction(ISD::FMAXNAN, MVT::f16, Legal);
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setOperationAction(ISD::FMINNAN, MVT::f32, Legal);
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setOperationAction(ISD::FMAXNAN, MVT::f32, Legal);
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setOperationAction(ISD::FMINNAN, MVT::v2f32, Legal);
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@ -6870,6 +6870,17 @@ class N3VSPat<SDNode OpNode, NeonI Inst>
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(v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
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SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
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class N3VSPatFP16<SDNode OpNode, NeonI Inst>
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: NEONFPPat<(f16 (OpNode HPR:$a, HPR:$b)),
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(EXTRACT_SUBREG
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(v4f16 (COPY_TO_REGCLASS (Inst
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(INSERT_SUBREG
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(v4f16 (COPY_TO_REGCLASS (v4f16 (IMPLICIT_DEF)), DPR_VFP2)),
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HPR:$a, ssub_0),
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(INSERT_SUBREG
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(v4f16 (COPY_TO_REGCLASS (v4f16 (IMPLICIT_DEF)), DPR_VFP2)),
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HPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
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class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
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: NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
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(EXTRACT_SUBREG
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@ -6912,6 +6923,8 @@ def : N3VSMulOpPat<fmul, fsub, VFMSfd>,
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Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
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def : N2VSPat<fabs, VABSfd>;
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def : N2VSPat<fneg, VNEGfd>;
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def : N3VSPatFP16<fmaxnan, VMAXhd>, Requires<[HasFullFP16]>;
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def : N3VSPatFP16<fminnan, VMINhd>, Requires<[HasFullFP16]>;
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def : N3VSPat<fmaxnan, VMAXfd>, Requires<[HasNEON]>;
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def : N3VSPat<fminnan, VMINfd>, Requires<[HasNEON]>;
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def : NVCVTFIPat<fp_to_sint, VCVTf2sd>;
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@ -482,9 +482,9 @@ defm VSELVS : vsel_inst<"vs", 0b01, 6>;
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multiclass vmaxmin_inst<string op, bit opc, SDNode SD> {
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let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in {
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def H : AHbInp<0b11101, 0b00, opc,
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(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
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(outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
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NoItinerary, !strconcat(op, ".f16\t$Sd, $Sn, $Sm"),
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[]>,
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[(set HPR:$Sd, (SD HPR:$Sn, HPR:$Sm))]>,
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Requires<[HasFullFP16]>;
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def S : ASbInp<0b11101, 0b00, opc,
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@ -28,6 +28,10 @@
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; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+fullfp16 -fp-contract=fast | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-FULLFP16-FAST
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mattr=+fullfp16 -fp-contract=fast | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-FULLFP16-FAST
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; TODO: we can't pass half-precision arguments as "half" types yet. We do
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; that for the time being by passing "float %f.coerce" and the necessary
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; bitconverts/truncates. But when we can pass half types, we do want to use
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; and test that here.
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define float @RetValBug(float %A.coerce) {
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entry:
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@ -477,9 +481,10 @@ entry:
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; CHECK-HARDFP-FULLFP16-FAST-NEXT: vmov.f32 s0, s2
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}
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; TODO:
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; 17. VMAXNM
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; 18. VMINNM
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; Tested in fp16-vminmaxnm.ll and fp16-vminmaxnm-safe.ll
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; 19. VMLA
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define float @VMLA(float %a.coerce, float %b.coerce, float %c.coerce) {
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366
test/CodeGen/ARM/fp16-vminmaxnm-safe.ll
Normal file
366
test/CodeGen/ARM/fp16-vminmaxnm-safe.ll
Normal file
@ -0,0 +1,366 @@
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; RUN: llc < %s -mtriple=armv8-eabi -mattr=+fullfp16 | FileCheck %s
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; RUN: llc < %s -mtriple thumbv7a -mattr=+fullfp16 | FileCheck %s
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; TODO: we can't pass half-precision arguments as "half" types yet. We do
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; that for the time being by passing "float %f.coerce" and the necessary
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; bitconverts/truncates. In these tests we pass i16 and use 1 bitconvert, which
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; is the shortest way to get a half type. But when we can pass half types, we
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; want to use that here.
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define half @fp16_vminnm_o(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vminnm_o:
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; CHECK-NOT: vminnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp olt half %0, %1
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%cond = select i1 %cmp, half %0, half %1
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ret half %cond
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}
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define half @fp16_vminnm_o_rev(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vminnm_o_rev:
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; CHECK-NOT: vminnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp ogt half %0, %1
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%cond = select i1 %cmp, half %0, half %1
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ret half %cond
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}
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define half @fp16_vminnm_u(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vminnm_u:
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; CHECK-NOT: vminnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp ult half %0, %1
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%cond = select i1 %cmp, half %0, half %1
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ret half %cond
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}
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define half @fp16_vminnm_ule(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vminnm_ule:
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; CHECK-NOT: vminnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp ule half %0, %1
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%cond = select i1 %cmp, half %0, half %1
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ret half %cond
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}
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define half @fp16_vminnm_u_rev(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vminnm_u_rev:
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; CHECK-NOT: vminnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp ugt half %0, %1
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%cond = select i1 %cmp, half %1, half %0
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ret half %cond
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}
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define half @fp16_vmaxnm_o(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vmaxnm_o:
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; CHECK-NOT: vmaxnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp ogt half %0, %1
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%cond = select i1 %cmp, half %0, half %1
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ret half %cond
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}
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define half @fp16_vmaxnm_oge(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vmaxnm_oge:
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; CHECK-NOT: vmaxnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp oge half %0, %1
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%cond = select i1 %cmp, half %0, half %1
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ret half %cond
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}
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define half @fp16_vmaxnm_o_rev(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vmaxnm_o_rev:
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; CHECK-NOT: vmaxnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp olt half %0, %1
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%cond = select i1 %cmp, half %1, half %0
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ret half %cond
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}
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define half @fp16_vmaxnm_ole_rev(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vmaxnm_ole_rev:
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; CHECK-NOT: vmaxnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp ole half %0, %1
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%cond = select i1 %cmp, half %1, half %0
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ret half %cond
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}
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define half @fp16_vmaxnm_u(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vmaxnm_u:
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; CHECK-NOT: vmaxnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp ugt half %0, %1
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%cond = select i1 %cmp, half %0, half %1
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ret half %cond
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}
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define half @fp16_vmaxnm_uge(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vmaxnm_uge:
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; CHECK-NOT: vmaxnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp uge half %0, %1
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%cond = select i1 %cmp, half %0, half %1
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ret half %cond
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}
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define half @fp16_vmaxnm_u_rev(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vmaxnm_u_rev:
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; CHECK-NOT: vmaxnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp ult half %0, %1
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%cond = select i1 %cmp, half %1, half %0
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ret half %cond
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}
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; known non-NaNs
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define half @fp16_vminnm_NNNo(i16 signext %a) {
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; CHECK-LABEL: fp16_vminnm_NNNo:
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S2:s[0-9]]], #1.200000e+01
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; CHECK: vmov.f16 [[S4:s[0-9]]], r{{.}}
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; CHECK: vminnm.f16 s2, [[S4]], [[S2]]
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; CHECK: vmin.f16 d0, d1, d0
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entry:
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%0 = bitcast i16 %a to half
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%cmp1 = fcmp olt half %0, 12.
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%cond1 = select i1 %cmp1, half %0, half 12.
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%cmp2 = fcmp olt half 34., %cond1
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%cond2 = select i1 %cmp2, half 34., half %cond1
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ret half %cond2
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}
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define half @fp16_vminnm_NNNo_rev(i16 signext %a) {
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; CHECK-LABEL: fp16_vminnm_NNNo_rev:
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
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; CHECK: vmin.f16 d0, d1, d0
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; CHECK: vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
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; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
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entry:
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%0 = bitcast i16 %a to half
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%cmp1 = fcmp ogt half %0, 56.
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%cond1 = select i1 %cmp1, half 56., half %0
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%cmp2 = fcmp ogt half 78., %cond1
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%cond2 = select i1 %cmp2, half %cond1, half 78.
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ret half %cond2
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}
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define half @fp16_vminnm_NNNu(i16 signext %b) {
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; CHECK-LABEL: fp16_vminnm_NNNu:
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S2:s[0-9]]], #1.200000e+01
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; CHECK: vmov.f16 [[S4:s[0-9]]], r{{.}}
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; CHECK: vminnm.f16 s2, [[S4]], [[S2]]
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; CHECK: vmin.f16 d0, d1, d0
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entry:
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%0 = bitcast i16 %b to half
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%cmp1 = fcmp ult half 12., %0
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%cond1 = select i1 %cmp1, half 12., half %0
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%cmp2 = fcmp ult half %cond1, 34.
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%cond2 = select i1 %cmp2, half %cond1, half 34.
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ret half %cond2
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}
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define half @fp16_vminnm_NNNule(i16 signext %b) {
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; CHECK-LABEL: fp16_vminnm_NNNule:
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; CHECK: vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S4:s[0-9]]], r{{.}}
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vminnm.f16 s2, [[S4]], [[S2]]
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; CHECK: vmin.f16 d0, d1, d0
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entry:
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%0 = bitcast i16 %b to half
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%cmp1 = fcmp ule half 34., %0
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%cond1 = select i1 %cmp1, half 34., half %0
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%cmp2 = fcmp ule half %cond1, 56.
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%cond2 = select i1 %cmp2, half %cond1, half 56.
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ret half %cond2
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}
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define half @fp16_vminnm_NNNu_rev(i16 signext %b) {
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; CHECK-LABEL: fp16_vminnm_NNNu_rev:
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
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; CHECK: vmin.f16 d0, d1, d0
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; CHECK: vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
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; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
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entry:
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%0 = bitcast i16 %b to half
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%cmp1 = fcmp ugt half 56., %0
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%cond1 = select i1 %cmp1, half %0, half 56.
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%cmp2 = fcmp ugt half %cond1, 78.
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%cond2 = select i1 %cmp2, half 78., half %cond1
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ret half %cond2
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}
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define half @fp16_vmaxnm_NNNo(i16 signext %a) {
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; CHECK-LABEL: fp16_vmaxnm_NNNo:
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S2:s[0-9]]], #1.200000e+01
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; CHECK: vmov.f16 [[S4:s[0-9]]], r{{.}}
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; CHECK: vmaxnm.f16 s2, [[S4]], [[S2]]
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; CHECK: vmax.f16 d0, d1, d0
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entry:
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%0 = bitcast i16 %a to half
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%cmp1 = fcmp ogt half %0, 12.
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%cond1 = select i1 %cmp1, half %0, half 12.
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%cmp2 = fcmp ogt half 34., %cond1
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%cond2 = select i1 %cmp2, half 34., half %cond1
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ret half %cond2
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}
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define half @fp16_vmaxnm_NNNoge(i16 signext %a) {
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; CHECK-LABEL: fp16_vmaxnm_NNNoge:
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; CHECK: vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S4:s[0-9]]], r{{.}}
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmaxnm.f16 s2, [[S4]], [[S2]]
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; CHECK: vmax.f16 d0, d1, d0
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entry:
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%0 = bitcast i16 %a to half
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%cmp1 = fcmp oge half %0, 34.
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%cond1 = select i1 %cmp1, half %0, half 34.
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%cmp2 = fcmp oge half 56., %cond1
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%cond2 = select i1 %cmp2, half 56., half %cond1
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ret half %cond2
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}
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define half @fp16_vmaxnm_NNNo_rev(i16 signext %a) {
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; CHECK-LABEL: fp16_vmaxnm_NNNo_rev:
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
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; CHECK: vmax.f16 d0, d1, d0
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; CHECK: vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
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entry:
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%0 = bitcast i16 %a to half
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%cmp1 = fcmp olt half %0, 56.
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%cond1 = select i1 %cmp1, half 56., half %0
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%cmp2 = fcmp olt half 78., %cond1
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%cond2 = select i1 %cmp2, half %cond1, half 78.
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ret half %cond2
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}
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define half @fp16_vmaxnm_NNNole_rev(i16 signext %a) {
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; CHECK-LABEL: fp16_vmaxnm_NNNole_rev:
|
||||
; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
|
||||
; CHECK: vmax.f16 d0, d1, d0
|
||||
; CHECK: vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%cmp1 = fcmp ole half %0, 78.
|
||||
%cond1 = select i1 %cmp1, half 78., half %0
|
||||
%cmp2 = fcmp ole half 90., %cond1
|
||||
%cond2 = select i1 %cmp2, half %cond1, half 90.
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vmaxnm_NNNu(i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vmaxnm_NNNu:
|
||||
; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], #1.200000e+01
|
||||
; CHECK: vmov.f16 [[S4:s[0-9]]], r{{.}}
|
||||
; CHECK: vmaxnm.f16 s2, [[S4]], [[S2]]
|
||||
; CHECK: vmax.f16 d0, d1, d0
|
||||
entry:
|
||||
%0 = bitcast i16 %b to half
|
||||
%cmp1 = fcmp ugt half 12., %0
|
||||
%cond1 = select i1 %cmp1, half 12., half %0
|
||||
%cmp2 = fcmp ugt half %cond1, 34.
|
||||
%cond2 = select i1 %cmp2, half %cond1, half 34.
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vmaxnm_NNNuge(i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vmaxnm_NNNuge:
|
||||
; CHECK: vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
|
||||
; CHECK: vmov.f16 [[S4:s[0-9]]], r{{.}}
|
||||
; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
|
||||
; CHECK: vmaxnm.f16 s2, [[S4]], [[S2]]
|
||||
; CHECK: vmax.f16 d0, d1, d0
|
||||
entry:
|
||||
%0 = bitcast i16 %b to half
|
||||
%cmp1 = fcmp uge half 34., %0
|
||||
%cond1 = select i1 %cmp1, half 34., half %0
|
||||
%cmp2 = fcmp uge half %cond1, 56.
|
||||
%cond2 = select i1 %cmp2, half %cond1, half 56.
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vminmaxnm_neg0(i16 signext %a) {
|
||||
; CHECK-LABEL: fp16_vminmaxnm_neg0:
|
||||
; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
|
||||
; CHECK: vminnm.f16 s2, [[S2]], [[S0]]
|
||||
; CHECK: vmax.f16 d0, d1, d0
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%cmp1 = fcmp olt half %0, -0.
|
||||
%cond1 = select i1 %cmp1, half %0, half -0.
|
||||
%cmp2 = fcmp ugt half %cond1, -0.
|
||||
%cond2 = select i1 %cmp2, half %cond1, half -0.
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vminmaxnm_e_0(i16 signext %a) {
|
||||
; CHECK-LABEL: fp16_vminmaxnm_e_0:
|
||||
; CHECK: vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmin.f16 d0, d0, d1
|
||||
; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%cmp1 = fcmp nsz ole half 0., %0
|
||||
%cond1 = select i1 %cmp1, half 0., half %0
|
||||
%cmp2 = fcmp nsz uge half 0., %cond1
|
||||
%cond2 = select i1 %cmp2, half 0., half %cond1
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vminmaxnm_e_neg0(i16 signext %a) {
|
||||
; CHECK-LABEL: fp16_vminmaxnm_e_neg0:
|
||||
; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
|
||||
; CHECK: vminnm.f16 s2, [[S2]], [[S0]]
|
||||
; CHECK: vmax.f16 d0, d1, d0
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%cmp1 = fcmp nsz ule half -0., %0
|
||||
%cond1 = select i1 %cmp1, half -0., half %0
|
||||
%cmp2 = fcmp nsz oge half -0., %cond1
|
||||
%cond2 = select i1 %cmp2, half -0., half %cond1
|
||||
ret half %cond2
|
||||
}
|
||||
418
test/CodeGen/ARM/fp16-vminmaxnm.ll
Normal file
418
test/CodeGen/ARM/fp16-vminmaxnm.ll
Normal file
@ -0,0 +1,418 @@
|
||||
; RUN: llc < %s -mtriple=arm-eabi -mattr=+fullfp16 -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck %s
|
||||
; RUN: llc < %s -mtriple thumbv7a -mattr=+fullfp16 -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck %s
|
||||
|
||||
; TODO: we can't pass half-precision arguments as "half" types yet. We do
|
||||
; that for the time being by passing "float %f.coerce" and the necessary
|
||||
; bitconverts/truncates. In these tests we pass i16 and use 1 bitconvert, which
|
||||
; is the shortest way to get a half type. But when we can pass half types, we
|
||||
; want to use that here.
|
||||
|
||||
define half @fp16_vminnm_o(i16 signext %a, i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vminnm_o:
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
|
||||
; CHECK: vminnm.f16 s0, [[S2]], [[S0]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%1 = bitcast i16 %b to half
|
||||
%cmp = fcmp fast olt half %0, %1
|
||||
%cond = select i1 %cmp, half %0, half %1
|
||||
ret half %cond
|
||||
}
|
||||
|
||||
define half @fp16_vminnm_o_rev(i16 signext %a, i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vminnm_o_rev:
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
|
||||
; CHECK: vminnm.f16 s0, [[S2]], [[S0]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%1 = bitcast i16 %b to half
|
||||
%cmp = fcmp fast ogt half %0, %1
|
||||
%cond = select i1 %cmp, half %1, half %0
|
||||
ret half %cond
|
||||
}
|
||||
|
||||
define half @fp16_vminnm_u(i16 signext %a, i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vminnm_u:
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
|
||||
; CHECK: vminnm.f16 s0, [[S2]], [[S0]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%1 = bitcast i16 %b to half
|
||||
%cmp = fcmp fast ult half %0, %1
|
||||
%cond = select i1 %cmp, half %0, half %1
|
||||
ret half %cond
|
||||
}
|
||||
|
||||
define half @fp16_vminnm_ule(i16 signext %a, i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vminnm_ule:
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
|
||||
; CHECK: vminnm.f16 s0, [[S2]], [[S0]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%1 = bitcast i16 %b to half
|
||||
%cmp = fcmp fast ule half %0, %1
|
||||
%cond = select i1 %cmp, half %0, half %1
|
||||
ret half %cond
|
||||
}
|
||||
|
||||
define half @fp16_vminnm_u_rev(i16 signext %a, i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vminnm_u_rev:
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
|
||||
; CHECK: vminnm.f16 s0, [[S2]], [[S0]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%1 = bitcast i16 %b to half
|
||||
%cmp = fcmp fast ugt half %0, %1
|
||||
%cond = select i1 %cmp, half %1, half %0
|
||||
ret half %cond
|
||||
}
|
||||
|
||||
define half @fp16_vmaxnm_o(i16 signext %a, i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vmaxnm_o:
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S2]], [[S0]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%1 = bitcast i16 %b to half
|
||||
%cmp = fcmp fast ogt half %0, %1
|
||||
%cond = select i1 %cmp, half %0, half %1
|
||||
ret half %cond
|
||||
}
|
||||
|
||||
define half @fp16_vmaxnm_oge(i16 signext %a, i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vmaxnm_oge:
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S2]], [[S0]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%1 = bitcast i16 %b to half
|
||||
%cmp = fcmp fast oge half %0, %1
|
||||
%cond = select i1 %cmp, half %0, half %1
|
||||
ret half %cond
|
||||
}
|
||||
|
||||
define half @fp16_vmaxnm_o_rev(i16 signext %a, i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vmaxnm_o_rev:
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S2]], [[S0]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%1 = bitcast i16 %b to half
|
||||
%cmp = fcmp fast olt half %0, %1
|
||||
%cond = select i1 %cmp, half %1, half %0
|
||||
ret half %cond
|
||||
}
|
||||
|
||||
define half @fp16_vmaxnm_ole_rev(i16 signext %a, i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vmaxnm_ole_rev:
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S2]], [[S0]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%1 = bitcast i16 %b to half
|
||||
%cmp = fcmp fast ole half %0, %1
|
||||
%cond = select i1 %cmp, half %1, half %0
|
||||
ret half %cond
|
||||
}
|
||||
|
||||
define half @fp16_vmaxnm_u(i16 signext %a, i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vmaxnm_u:
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S2]], [[S0]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%1 = bitcast i16 %b to half
|
||||
%cmp = fcmp fast ugt half %0, %1
|
||||
%cond = select i1 %cmp, half %0, half %1
|
||||
ret half %cond
|
||||
}
|
||||
|
||||
define half @fp16_vmaxnm_uge(i16 signext %a, i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vmaxnm_uge:
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S2]], [[S0]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%1 = bitcast i16 %b to half
|
||||
%cmp = fcmp fast uge half %0, %1
|
||||
%cond = select i1 %cmp, half %0, half %1
|
||||
ret half %cond
|
||||
}
|
||||
|
||||
define half @fp16_vmaxnm_u_rev(i16 signext %a, i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vmaxnm_u_rev:
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S2]], [[S0]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%1 = bitcast i16 %b to half
|
||||
%cmp = fcmp fast ult half %0, %1
|
||||
%cond = select i1 %cmp, half %1, half %0
|
||||
ret half %cond
|
||||
}
|
||||
|
||||
; known non-NaNs
|
||||
|
||||
define half @fp16_vminnm_NNNo(i16 signext %a) {
|
||||
; CHECK-LABEL: fp16_vminnm_NNNo:
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], #1.200000e+01
|
||||
; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%cmp1 = fcmp fast olt half %0, 12.
|
||||
%cond1 = select i1 %cmp1, half %0, half 12.
|
||||
%cmp2 = fcmp fast olt half 34., %cond1
|
||||
%cond2 = select i1 %cmp2, half 34., half %cond1
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vminnm_NNNo_rev(i16 signext %a) {
|
||||
; CHECK-LABEL: fp16_vminnm_NNNo_rev:
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%cmp1 = fcmp fast ogt half %0, 56.
|
||||
%cond1 = select i1 %cmp1, half 56., half %0
|
||||
%cmp2 = fcmp fast ogt half 78., %cond1
|
||||
%cond2 = select i1 %cmp2, half %cond1, half 78.
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vminnm_NNNu(i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vminnm_NNNu:
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], #1.200000e+01
|
||||
; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
|
||||
entry:
|
||||
%0 = bitcast i16 %b to half
|
||||
%cmp1 = fcmp fast ult half 12., %0
|
||||
%cond1 = select i1 %cmp1, half 12., half %0
|
||||
%cmp2 = fcmp fast ult half %cond1, 34.
|
||||
%cond2 = select i1 %cmp2, half %cond1, half 34.
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vminnm_NNNule(i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vminnm_NNNule:
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
|
||||
entry:
|
||||
%0 = bitcast i16 %b to half
|
||||
%cmp1 = fcmp fast ule half 34., %0
|
||||
%cond1 = select i1 %cmp1, half 34., half %0
|
||||
%cmp2 = fcmp fast ule half %cond1, 56.
|
||||
%cond2 = select i1 %cmp2, half %cond1, half 56.
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vminnm_NNNu_rev(i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vminnm_NNNu_rev:
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
|
||||
entry:
|
||||
%0 = bitcast i16 %b to half
|
||||
%cmp1 = fcmp fast ugt half 56., %0
|
||||
%cond1 = select i1 %cmp1, half %0, half 56.
|
||||
%cmp2 = fcmp fast ugt half %cond1, 78.
|
||||
%cond2 = select i1 %cmp2, half 78., half %cond1
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vmaxnm_NNNo(i16 signext %a) {
|
||||
; CHECK-LABEL: fp16_vmaxnm_NNNo:
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], #1.200000e+01
|
||||
; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%cmp1 = fcmp fast ogt half %0, 12.
|
||||
%cond1 = select i1 %cmp1, half %0, half 12.
|
||||
%cmp2 = fcmp fast ogt half 34., %cond1
|
||||
%cond2 = select i1 %cmp2, half 34., half %cond1
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vmaxnm_NNNoge(i16 signext %a) {
|
||||
; CHECK-LABEL: fp16_vmaxnm_NNNoge:
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%cmp1 = fcmp fast oge half %0, 34.
|
||||
%cond1 = select i1 %cmp1, half %0, half 34.
|
||||
%cmp2 = fcmp fast oge half 56., %cond1
|
||||
%cond2 = select i1 %cmp2, half 56., half %cond1
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vmaxnm_NNNo_rev(i16 signext %a) {
|
||||
; CHECK-LABEL: fp16_vmaxnm_NNNo_rev:
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%cmp1 = fcmp fast olt half %0, 56.
|
||||
%cond1 = select i1 %cmp1, half 56., half %0
|
||||
%cmp2 = fcmp fast olt half 78., %cond1
|
||||
%cond2 = select i1 %cmp2, half %cond1, half 78.
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vmaxnm_NNNole_rev(i16 signext %a) {
|
||||
; CHECK-LABEL: fp16_vmaxnm_NNNole_rev:
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%cmp1 = fcmp fast ole half %0, 78.
|
||||
%cond1 = select i1 %cmp1, half 78., half %0
|
||||
%cmp2 = fcmp fast ole half 90., %cond1
|
||||
%cond2 = select i1 %cmp2, half %cond1, half 90.
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vmaxnm_NNNu(i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vmaxnm_NNNu:
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], #1.200000e+01
|
||||
; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
|
||||
entry:
|
||||
%0 = bitcast i16 %b to half
|
||||
%cmp1 = fcmp fast ugt half 12., %0
|
||||
%cond1 = select i1 %cmp1, half 12., half %0
|
||||
%cmp2 = fcmp fast ugt half %cond1, 34.
|
||||
%cond2 = select i1 %cmp2, half %cond1, half 34.
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vmaxnm_NNNuge(i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vmaxnm_NNNuge:
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
|
||||
entry:
|
||||
%0 = bitcast i16 %b to half
|
||||
%cmp1 = fcmp fast uge half 34., %0
|
||||
%cond1 = select i1 %cmp1, half 34., half %0
|
||||
%cmp2 = fcmp fast uge half %cond1, 56.
|
||||
%cond2 = select i1 %cmp2, half %cond1, half 56.
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vmaxnm_NNNu_rev(i16 signext %b) {
|
||||
; CHECK-LABEL: fp16_vmaxnm_NNNu_rev:
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
|
||||
; CHECK: vldr.16 s2, .LCPI{{.*}}
|
||||
; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
|
||||
entry:
|
||||
%0 = bitcast i16 %b to half
|
||||
%cmp1 = fcmp fast ult half 56., %0
|
||||
%cond1 = select i1 %cmp1, half %0, half 56.
|
||||
%cmp2 = fcmp fast ult half %cond1, 78.
|
||||
%cond2 = select i1 %cmp2, half 78., half %cond1
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vminmaxnm_0(i16 signext %a) {
|
||||
; CHECK-LABEL: fp16_vminmaxnm_0:
|
||||
; CHECK: vldr.16 s0, .LCPI{{.*}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
|
||||
; CHECK: vminnm.f16 s2, s2, s0
|
||||
; CHECK: vmaxnm.f16 s0, [[S2]], [[S0]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%cmp1 = fcmp fast olt half %0, 0.
|
||||
%cond1 = select i1 %cmp1, half %0, half 0.
|
||||
%cmp2 = fcmp fast ogt half %cond1, 0.
|
||||
%cond2 = select i1 %cmp2, half %cond1, half 0.
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vminmaxnm_neg0(i16 signext %a) {
|
||||
; CHECK-LABEL: fp16_vminmaxnm_neg0:
|
||||
; CHECK: vldr.16 s0, .LCPI{{.*}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
|
||||
; CHECK: vminnm.f16 s2, s2, s0
|
||||
; CHECK: vmaxnm.f16 s0, [[S2]], [[S0]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%cmp1 = fcmp fast olt half %0, -0.
|
||||
%cond1 = select i1 %cmp1, half %0, half -0.
|
||||
%cmp2 = fcmp fast ugt half %cond1, -0.
|
||||
%cond2 = select i1 %cmp2, half %cond1, half -0.
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vminmaxnm_e_0(i16 signext %a) {
|
||||
; CHECK-LABEL: fp16_vminmaxnm_e_0:
|
||||
; CHECK: vldr.16 s0, .LCPI{{.*}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
|
||||
; CHECK: vminnm.f16 s2, s2, s0
|
||||
; CHECK: vmaxnm.f16 s0, [[S2]], [[S0]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%cmp1 = fcmp fast ule half 0., %0
|
||||
%cond1 = select i1 %cmp1, half 0., half %0
|
||||
%cmp2 = fcmp fast uge half 0., %cond1
|
||||
%cond2 = select i1 %cmp2, half 0., half %cond1
|
||||
ret half %cond2
|
||||
}
|
||||
|
||||
define half @fp16_vminmaxnm_e_neg0(i16 signext %a) {
|
||||
; CHECK-LABEL: fp16_vminmaxnm_e_neg0:
|
||||
; CHECK: vldr.16 s0, .LCPI{{.*}}
|
||||
; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
|
||||
; CHECK: vminnm.f16 s2, s2, s0
|
||||
; CHECK: vmaxnm.f16 s0, [[S2]], [[S0]]
|
||||
entry:
|
||||
%0 = bitcast i16 %a to half
|
||||
%cmp1 = fcmp fast ule half -0., %0
|
||||
%cond1 = select i1 %cmp1, half -0., half %0
|
||||
%cmp2 = fcmp fast oge half -0., %cond1
|
||||
%cond2 = select i1 %cmp2, half -0., half %cond1
|
||||
ret half %cond2
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user