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[X86] Use LivePhysRegs in X86FixupBWInsts.
Kill-flags, which computeRegisterLiveness uses, are not reliable. LivePhysRegs is. Differential Revision: http://reviews.llvm.org/D19472 llvm-svn: 267495
This commit is contained in:
Ahmed Bougacha
parent
504105c02c
commit
b6c12fe106
@ -49,7 +49,7 @@
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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@ -81,7 +81,7 @@ class FixupBWInstPass : public MachineFunctionPass {
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/// \brief Loop over all of the instructions in the basic block
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/// replacing applicable byte or word instructions with better
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/// alternatives.
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void processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB) const;
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void processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
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/// \brief This sets the \p SuperDestReg to the 32 bit super reg
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/// of the original destination register of the MachineInstr
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@ -128,6 +128,9 @@ private:
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/// Machine loop info used for guiding some heruistics.
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MachineLoopInfo *MLI;
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/// Register Liveness information after the current instruction.
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LivePhysRegs LiveRegs;
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};
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char FixupBWInstPass::ID = 0;
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}
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@ -142,6 +145,7 @@ bool FixupBWInstPass::runOnMachineFunction(MachineFunction &MF) {
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TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
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OptForSize = MF.getFunction()->optForSize();
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MLI = &getAnalysis<MachineLoopInfo>();
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LiveRegs.init(&TII->getRegisterInfo());
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DEBUG(dbgs() << "Start X86FixupBWInsts\n";);
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@ -181,11 +185,7 @@ bool FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI,
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if (getX86SubSuperRegister(SuperDestReg, OrigDestSize) != OrigDestReg)
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return false;
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MachineBasicBlock::LivenessQueryResult LQR =
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OrigMI->getParent()->computeRegisterLiveness(&TII->getRegisterInfo(),
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SuperDestReg, OrigMI);
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if (LQR != MachineBasicBlock::LQR_Dead)
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if (LiveRegs.contains(SuperDestReg))
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return false;
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if (OrigDestSize == 8) {
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@ -194,9 +194,7 @@ bool FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI,
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// whether the super-register is dead.
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unsigned UpperByteReg = getX86SubSuperRegister(SuperDestReg, 8, true);
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LQR = OrigMI->getParent()->computeRegisterLiveness(&TII->getRegisterInfo(),
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UpperByteReg, OrigMI);
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if (LQR != MachineBasicBlock::LQR_Dead)
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if (LiveRegs.contains(UpperByteReg))
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return false;
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}
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@ -229,7 +227,7 @@ MachineInstr *FixupBWInstPass::tryReplaceLoad(unsigned New32BitOpcode,
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}
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void FixupBWInstPass::processBasicBlock(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock &MBB) {
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// This algorithm doesn't delete the instructions it is replacing
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// right away. By leaving the existing instructions in place, the
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@ -243,9 +241,14 @@ void FixupBWInstPass::processBasicBlock(MachineFunction &MF,
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// from making it seem as if the larger register might be live.
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SmallVector<std::pair<MachineInstr *, MachineInstr *>, 8> MIReplacements;
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for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
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// Start computing liveness for this block. We iterate from the end to be able
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// to update this for each instruction.
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LiveRegs.clear();
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LiveRegs.addLiveOuts(&MBB);
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for (auto I = MBB.rbegin(); I != MBB.rend(); ++I) {
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MachineInstr *NewMI = nullptr;
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MachineInstr *MI = I;
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MachineInstr *MI = &*I;
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// See if this is an instruction of the type we are currently looking for.
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switch (MI->getOpcode()) {
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@ -275,6 +278,9 @@ void FixupBWInstPass::processBasicBlock(MachineFunction &MF,
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if (NewMI)
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MIReplacements.push_back(std::make_pair(MI, NewMI));
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// We're done with this instruction, update liveness for the next one.
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LiveRegs.stepBackward(*MI);
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}
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while (!MIReplacements.empty()) {
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@ -1,6 +1,6 @@
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx -fixup-byte-word-insts=1 < %s | FileCheck -check-prefix=CHECK -check-prefix=BWON %s
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx -fixup-byte-word-insts=0 < %s | FileCheck -check-prefix=CHECK -check-prefix=BWOFF %s
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx -addr-sink-using-gep=1 < %s | FileCheck %s
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx -addr-sink-using-gep=1 < %s | FileCheck -check-prefix=CHECK -check-prefix=BWON %s
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%struct.A = type { i8, i8, i8, i8, i8, i8, i8, i8 }
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%struct.B = type { i32, i32, i32, i32, i32, i32, i32, i32 }
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@ -185,7 +185,8 @@ define void @merge_loads_i16(i32 %count, %struct.A* noalias nocapture %q, %struc
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; BWON: movzbl
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; BWOFF: movb
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; CHECK: movb
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; CHECK: movb
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; BWON: movzbl
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; BWOFF: movb
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; CHECK: movb
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; CHECK: ret
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define void @no_merge_loads(i32 %count, %struct.A* noalias nocapture %q, %struct.A* noalias nocapture %p) nounwind uwtable noinline ssp {
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@ -340,8 +341,9 @@ block4: ; preds = %4, %.lr.ph
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; Make sure that we merge the consecutive load/store sequence below and use a
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; word (16 bit) instead of a byte copy.
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; CHECK-LABEL: MergeLoadStoreBaseIndexOffset:
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; CHECK: movw (%{{.*}},%{{.*}}), [[REG:%[a-z]+]]
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; CHECK: movw [[REG]], (%{{.*}})
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; BWON: movzwl (%{{.*}},%{{.*}}), %e[[REG:[a-z]+]]
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; BWOFF: movw (%{{.*}},%{{.*}}), %[[REG:[a-z]+]]
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; CHECK: movw %[[REG]], (%{{.*}})
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define void @MergeLoadStoreBaseIndexOffset(i64* %a, i8* %b, i8* %c, i32 %n) {
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br label %1
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@ -372,8 +374,9 @@ define void @MergeLoadStoreBaseIndexOffset(i64* %a, i8* %b, i8* %c, i32 %n) {
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; word (16 bit) instead of a byte copy even if there are intermediate sign
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; extensions.
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; CHECK-LABEL: MergeLoadStoreBaseIndexOffsetSext:
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; CHECK: movw (%{{.*}},%{{.*}}), [[REG:%[a-z]+]]
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; CHECK: movw [[REG]], (%{{.*}})
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; BWON: movzwl (%{{.*}},%{{.*}}), %e[[REG:[a-z]+]]
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; BWOFF: movw (%{{.*}},%{{.*}}), %[[REG:[a-z]+]]
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; CHECK: movw %[[REG]], (%{{.*}})
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define void @MergeLoadStoreBaseIndexOffsetSext(i8* %a, i8* %b, i8* %c, i32 %n) {
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br label %1
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@ -11,8 +11,6 @@ target triple = "x86_64-apple-macosx10.8.0"
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; This has byte loads interspersed with byte stores, in a single
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; basic-block loop. The upper portion should be dead, so the movb loads
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; should have been changed into movzbl instead.
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; TODO: The second movb load doesn't get fixed due to register liveness
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; not being accurate enough.
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; CHECK-LABEL: foo1
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; load:
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; BWON: movzbl
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@ -20,7 +18,8 @@ target triple = "x86_64-apple-macosx10.8.0"
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; store:
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; CHECK: movb
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; load:
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; CHECK: movb
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; BWON: movzbl
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; BWOFF: movb
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; store:
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; CHECK: movb
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; CHECK: ret
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@ -59,8 +58,6 @@ a4: ; preds = %4, %.lr.ph
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; This has word loads interspersed with word stores.
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; The upper portion should be dead, so the movw loads should have
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; been changed into movzwl instead.
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; TODO: The second movw load doesn't get fixed due to register liveness
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; not being accurate enough.
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; CHECK-LABEL: foo2
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; load:
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; BWON: movzwl
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@ -68,7 +65,8 @@ a4: ; preds = %4, %.lr.ph
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; store:
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; CHECK: movw
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; load:
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; CHECK: movw
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; BWON: movzwl
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; BWOFF: movw
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; store:
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; CHECK: movw
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; CHECK: ret
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@ -6,7 +6,10 @@
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; RUN: FileCheck -check-prefix=CHECK -check-prefix=BWOFF %s
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; RUN: llc < %s -mtriple=i686-unknown-linux-gnu -fixup-byte-word-insts=1 | \
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; RUN: FileCheck -check-prefix=CHECK -check-prefix=BWON %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck -check-prefix=DARWIN %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -fixup-byte-word-insts=0 | \
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; RUN: FileCheck -check-prefix=DARWIN -check-prefix=DARWIN-BWOFF %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -fixup-byte-word-insts=1 | \
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; RUN: FileCheck -check-prefix=DARWIN -check-prefix=DARWIN-BWON %s
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@x = common global i32 0, align 4
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@ -84,7 +87,8 @@ entry:
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; Except on Darwin, for legay reasons.
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; DARWIN-LABEL: unsigned_i16:
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; DARWIN: movw
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; DARWIN-BWOFF: movw
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; DARWIN-BWON: movzwl
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; DARWIN-NEXT: addw
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; DARWIN-NEXT: movzwl
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; DARWIN-NEXT: ret
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