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https://github.com/RPCS3/llvm-mirror.git
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[Hexagon] Adding xtype shift instructions.
llvm-svn: 224604
This commit is contained in:
Colin LeMahieu
parent
16013f08b8
commit
b6c1e97753
@ -3410,6 +3410,17 @@ def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>;
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def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>;
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def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>;
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// Y4_trace: Send value to etm trace.
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let isSoloAX = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
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def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs),
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"trace($Rs)"> {
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bits<5> Rs;
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let IClass = 0b0110;
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let Inst{27-21} = 0b0010010;
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let Inst{20-16} = Rs;
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}
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// TFRI64 - assembly mapped.
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let isReMaterializable = 1 in
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def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
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@ -4279,6 +4290,193 @@ def : Pat<(HexagonWrapperJT tjumptable:$dst),
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(i32 (CONST32_set_jt tjumptable:$dst))>;
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// XTYPE/SHIFT
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//
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//===----------------------------------------------------------------------===//
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// Template Class
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// Shift by immediate/register and accumulate/logical
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//===----------------------------------------------------------------------===//
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// Rx[+-&|]=asr(Rs,#u5)
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// Rx[+-&|^]=lsr(Rs,#u5)
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// Rx[+-&|^]=asl(Rs,#u5)
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let hasNewValue = 1, opNewValue = 0 in
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class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1,
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SDNode OpNode2, bits<3> majOp, bits<2> minOp>
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: SInst_acc<(outs IntRegs:$Rx),
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(ins IntRegs:$src1, IntRegs:$Rs, u5Imm:$u5),
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"$Rx "#opc2#opc1#"($Rs, #$u5)",
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[(set (i32 IntRegs:$Rx),
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(OpNode2 (i32 IntRegs:$src1),
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(OpNode1 (i32 IntRegs:$Rs), u5ImmPred:$u5)))],
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"$src1 = $Rx", S_2op_tc_2_SLOT23> {
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bits<5> Rx;
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bits<5> Rs;
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bits<5> u5;
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let IClass = 0b1000;
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let Inst{27-24} = 0b1110;
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let Inst{23-22} = majOp{2-1};
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let Inst{13} = 0b0;
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let Inst{7} = majOp{0};
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let Inst{6-5} = minOp;
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let Inst{4-0} = Rx;
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let Inst{20-16} = Rs;
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let Inst{12-8} = u5;
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}
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// Rx[+-&|]=asr(Rs,Rt)
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// Rx[+-&|^]=lsr(Rs,Rt)
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// Rx[+-&|^]=asl(Rs,Rt)
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let hasNewValue = 1, opNewValue = 0 in
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class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1,
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SDNode OpNode2, bits<2> majOp, bits<2> minOp>
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: SInst_acc<(outs IntRegs:$Rx),
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(ins IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt),
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"$Rx "#opc2#opc1#"($Rs, $Rt)",
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[(set (i32 IntRegs:$Rx),
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(OpNode2 (i32 IntRegs:$src1),
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(OpNode1 (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))],
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"$src1 = $Rx", S_3op_tc_2_SLOT23 > {
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bits<5> Rx;
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bits<5> Rs;
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bits<5> Rt;
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let IClass = 0b1100;
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let Inst{27-24} = 0b1100;
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let Inst{23-22} = majOp;
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let Inst{7-6} = minOp;
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let Inst{4-0} = Rx;
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let Inst{20-16} = Rs;
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let Inst{12-8} = Rt;
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}
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// Rxx[+-&|]=asr(Rss,#u6)
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// Rxx[+-&|^]=lsr(Rss,#u6)
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// Rxx[+-&|^]=asl(Rss,#u6)
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class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1,
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SDNode OpNode2, bits<3> majOp, bits<2> minOp>
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: SInst_acc<(outs DoubleRegs:$Rxx),
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(ins DoubleRegs:$src1, DoubleRegs:$Rss, u6Imm:$u6),
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"$Rxx "#opc2#opc1#"($Rss, #$u6)",
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[(set (i64 DoubleRegs:$Rxx),
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(OpNode2 (i64 DoubleRegs:$src1),
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(OpNode1 (i64 DoubleRegs:$Rss), u6ImmPred:$u6)))],
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"$src1 = $Rxx", S_2op_tc_2_SLOT23> {
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bits<5> Rxx;
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bits<5> Rss;
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bits<6> u6;
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let IClass = 0b1000;
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let Inst{27-24} = 0b0010;
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let Inst{23-22} = majOp{2-1};
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let Inst{7} = majOp{0};
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let Inst{6-5} = minOp;
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let Inst{4-0} = Rxx;
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let Inst{20-16} = Rss;
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let Inst{13-8} = u6;
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}
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// Rxx[+-&|]=asr(Rss,Rt)
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// Rxx[+-&|^]=lsr(Rss,Rt)
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// Rxx[+-&|^]=asl(Rss,Rt)
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// Rxx[+-&|^]=lsl(Rss,Rt)
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class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1,
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SDNode OpNode2, bits<3> majOp, bits<2> minOp>
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: SInst_acc<(outs DoubleRegs:$Rxx),
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(ins DoubleRegs:$src1, DoubleRegs:$Rss, IntRegs:$Rt),
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"$Rxx "#opc2#opc1#"($Rss, $Rt)",
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[(set (i64 DoubleRegs:$Rxx),
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(OpNode2 (i64 DoubleRegs:$src1),
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(OpNode1 (i64 DoubleRegs:$Rss), (i32 IntRegs:$Rt))))],
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"$src1 = $Rxx", S_3op_tc_2_SLOT23> {
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bits<5> Rxx;
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bits<5> Rss;
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bits<5> Rt;
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let IClass = 0b1100;
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let Inst{27-24} = 0b1011;
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let Inst{23-21} = majOp;
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let Inst{20-16} = Rss;
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let Inst{12-8} = Rt;
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let Inst{7-6} = minOp;
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let Inst{4-0} = Rxx;
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}
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//===----------------------------------------------------------------------===//
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// Multi-class for the shift instructions with logical/arithmetic operators.
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//===----------------------------------------------------------------------===//
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multiclass xtype_imm_base<string OpcStr1, string OpcStr2, SDNode OpNode1,
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SDNode OpNode2, bits<3> majOp, bits<2> minOp > {
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def _i_r#NAME : T_shift_imm_acc_r< OpcStr1, OpcStr2, OpNode1,
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OpNode2, majOp, minOp >;
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def _i_p#NAME : T_shift_imm_acc_p< OpcStr1, OpcStr2, OpNode1,
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OpNode2, majOp, minOp >;
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}
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multiclass xtype_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
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let AddedComplexity = 100 in
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defm _acc : xtype_imm_base< opc1, "+= ", OpNode, add, 0b001, minOp>;
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defm _nac : xtype_imm_base< opc1, "-= ", OpNode, sub, 0b000, minOp>;
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defm _and : xtype_imm_base< opc1, "&= ", OpNode, and, 0b010, minOp>;
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defm _or : xtype_imm_base< opc1, "|= ", OpNode, or, 0b011, minOp>;
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}
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multiclass xtype_xor_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
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let AddedComplexity = 100 in
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defm _xacc : xtype_imm_base< opc1, "^= ", OpNode, xor, 0b100, minOp>;
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}
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let isCodeGenOnly = 0 in {
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defm S2_asr : xtype_imm_acc<"asr", sra, 0b00>;
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defm S2_lsr : xtype_imm_acc<"lsr", srl, 0b01>,
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xtype_xor_imm_acc<"lsr", srl, 0b01>;
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defm S2_asl : xtype_imm_acc<"asl", shl, 0b10>,
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xtype_xor_imm_acc<"asl", shl, 0b10>;
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}
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multiclass xtype_reg_acc_r<string opc1, SDNode OpNode, bits<2>minOp> {
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let AddedComplexity = 100 in
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def _acc : T_shift_reg_acc_r <opc1, "+= ", OpNode, add, 0b11, minOp>;
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def _nac : T_shift_reg_acc_r <opc1, "-= ", OpNode, sub, 0b10, minOp>;
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def _and : T_shift_reg_acc_r <opc1, "&= ", OpNode, and, 0b01, minOp>;
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def _or : T_shift_reg_acc_r <opc1, "|= ", OpNode, or, 0b00, minOp>;
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}
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multiclass xtype_reg_acc_p<string opc1, SDNode OpNode, bits<2>minOp> {
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let AddedComplexity = 100 in
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def _acc : T_shift_reg_acc_p <opc1, "+= ", OpNode, add, 0b110, minOp>;
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def _nac : T_shift_reg_acc_p <opc1, "-= ", OpNode, sub, 0b100, minOp>;
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def _and : T_shift_reg_acc_p <opc1, "&= ", OpNode, and, 0b010, minOp>;
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def _or : T_shift_reg_acc_p <opc1, "|= ", OpNode, or, 0b000, minOp>;
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def _xor : T_shift_reg_acc_p <opc1, "^= ", OpNode, xor, 0b011, minOp>;
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}
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multiclass xtype_reg_acc<string OpcStr, SDNode OpNode, bits<2> minOp > {
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defm _r_r : xtype_reg_acc_r <OpcStr, OpNode, minOp>;
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defm _r_p : xtype_reg_acc_p <OpcStr, OpNode, minOp>;
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}
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let isCodeGenOnly = 0 in {
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defm S2_asl : xtype_reg_acc<"asl", shl, 0b10>;
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defm S2_asr : xtype_reg_acc<"asr", sra, 0b00>;
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defm S2_lsr : xtype_reg_acc<"lsr", srl, 0b01>;
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defm S2_lsl : xtype_reg_acc<"lsl", shl, 0b11>;
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}
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// Multi-class for logical operators :
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// Shift by immediate/register and accumulate/logical
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4
test/MC/Disassembler/Hexagon/system_user.txt
Normal file
4
test/MC/Disassembler/Hexagon/system_user.txt
Normal file
@ -0,0 +1,4 @@
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# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
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0x00 0xc0 0x51 0x62
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# CHECK: trace(r17)
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@ -12,9 +12,137 @@
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# CHECK: r17 = lsr(r21, #31)
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0x51 0xdf 0x15 0x8c
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# CHECK: r17 = asl(r21, #31)
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0x10 0xdf 0x14 0x82
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# CHECK: r17:16 -= asr(r21:20, #31)
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0x30 0xdf 0x14 0x82
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# CHECK: r17:16 -= lsr(r21:20, #31)
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0x50 0xdf 0x14 0x82
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# CHECK: r17:16 -= asl(r21:20, #31)
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0x90 0xdf 0x14 0x82
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# CHECK: r17:16 += asr(r21:20, #31)
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0xb0 0xdf 0x14 0x82
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# CHECK: r17:16 += lsr(r21:20, #31)
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0xd0 0xdf 0x14 0x82
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# CHECK: r17:16 += asl(r21:20, #31)
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0x11 0xdf 0x15 0x8e
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# CHECK: r17 -= asr(r21, #31)
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0x31 0xdf 0x15 0x8e
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# CHECK: r17 -= lsr(r21, #31)
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0x51 0xdf 0x15 0x8e
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# CHECK: r17 -= asl(r21, #31)
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0x91 0xdf 0x15 0x8e
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# CHECK: r17 += asr(r21, #31)
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0xb1 0xdf 0x15 0x8e
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# CHECK: r17 += lsr(r21, #31)
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0xd1 0xdf 0x15 0x8e
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# CHECK: r17 += asl(r21, #31)
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0xf1 0xd5 0x1f 0xc4
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# CHECK: r17 = addasl(r21, r31, #7)
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0x10 0xdf 0x54 0x82
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# CHECK: r17:16 &= asr(r21:20, #31)
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0x30 0xdf 0x54 0x82
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# CHECK: r17:16 &= lsr(r21:20, #31)
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0x50 0xdf 0x54 0x82
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# CHECK: r17:16 &= asl(r21:20, #31)
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0x90 0xdf 0x54 0x82
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# CHECK: r17:16 |= asr(r21:20, #31)
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0xb0 0xdf 0x54 0x82
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# CHECK: r17:16 |= lsr(r21:20, #31)
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0xd0 0xdf 0x54 0x82
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# CHECK: r17:16 |= asl(r21:20, #31)
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0x30 0xdf 0x94 0x82
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# CHECK: r17:16 ^= lsr(r21:20, #31)
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0x50 0xdf 0x94 0x82
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# CHECK: r17:16 ^= asl(r21:20, #31)
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0x11 0xdf 0x55 0x8e
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# CHECK: r17 &= asr(r21, #31)
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0x31 0xdf 0x55 0x8e
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# CHECK: r17 &= lsr(r21, #31)
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0x51 0xdf 0x55 0x8e
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# CHECK: r17 &= asl(r21, #31)
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0x91 0xdf 0x55 0x8e
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# CHECK: r17 |= asr(r21, #31)
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0xb1 0xdf 0x55 0x8e
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# CHECK: r17 |= lsr(r21, #31)
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0xd1 0xdf 0x55 0x8e
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# CHECK: r17 |= asl(r21, #31)
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0x31 0xdf 0x95 0x8e
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# CHECK: r17 ^= lsr(r21, #31)
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0x51 0xdf 0x95 0x8e
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# CHECK: r17 ^= asl(r21, #31)
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0x11 0xdf 0x55 0x8c
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# CHECK: r17 = asr(r21, #31):rnd
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0x51 0xdf 0x55 0x8c
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# CHECK: r17 = asl(r21, #31):sat
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0x10 0xdf 0x94 0xcb
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# CHECK: r17:16 -= asr(r21:20, r31)
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0x50 0xdf 0x94 0xcb
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# CHECK: r17:16 -= lsr(r21:20, r31)
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0x90 0xdf 0x94 0xcb
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# CHECK: r17:16 -= asl(r21:20, r31)
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0xd0 0xdf 0x94 0xcb
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# CHECK: r17:16 -= lsl(r21:20, r31)
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0x10 0xdf 0xd4 0xcb
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# CHECK: r17:16 += asr(r21:20, r31)
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0x50 0xdf 0xd4 0xcb
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# CHECK: r17:16 += lsr(r21:20, r31)
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0x90 0xdf 0xd4 0xcb
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# CHECK: r17:16 += asl(r21:20, r31)
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0xd0 0xdf 0xd4 0xcb
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# CHECK: r17:16 += lsl(r21:20, r31)
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0x11 0xdf 0x95 0xcc
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# CHECK: r17 -= asr(r21, r31)
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0x51 0xdf 0x95 0xcc
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# CHECK: r17 -= lsr(r21, r31)
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0x91 0xdf 0x95 0xcc
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# CHECK: r17 -= asl(r21, r31)
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0xd1 0xdf 0x95 0xcc
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# CHECK: r17 -= lsl(r21, r31)
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0x11 0xdf 0xd5 0xcc
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# CHECK: r17 += asr(r21, r31)
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0x51 0xdf 0xd5 0xcc
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# CHECK: r17 += lsr(r21, r31)
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0x91 0xdf 0xd5 0xcc
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# CHECK: r17 += asl(r21, r31)
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0xd1 0xdf 0xd5 0xcc
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# CHECK: r17 += lsl(r21, r31)
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0x10 0xdf 0x14 0xcb
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# CHECK: r17:16 |= asr(r21:20, r31)
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0x50 0xdf 0x14 0xcb
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# CHECK: r17:16 |= lsr(r21:20, r31)
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0x90 0xdf 0x14 0xcb
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# CHECK: r17:16 |= asl(r21:20, r31)
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0xd0 0xdf 0x14 0xcb
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# CHECK: r17:16 |= lsl(r21:20, r31)
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0x10 0xdf 0x54 0xcb
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# CHECK: r17:16 &= asr(r21:20, r31)
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0x50 0xdf 0x54 0xcb
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# CHECK: r17:16 &= lsr(r21:20, r31)
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0x90 0xdf 0x54 0xcb
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# CHECK: r17:16 &= asl(r21:20, r31)
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0xd0 0xdf 0x54 0xcb
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# CHECK: r17:16 &= lsl(r21:20, r31)
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0x10 0xdf 0x74 0xcb
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# CHECK: r17:16 ^= asr(r21:20, r31)
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0x50 0xdf 0x74 0xcb
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# CHECK: r17:16 ^= lsr(r21:20, r31)
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0x90 0xdf 0x74 0xcb
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# CHECK: r17:16 ^= asl(r21:20, r31)
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0xd0 0xdf 0x74 0xcb
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# CHECK: r17:16 ^= lsl(r21:20, r31)
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0x11 0xdf 0x15 0xcc
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# CHECK: r17 |= asr(r21, r31)
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0x51 0xdf 0x15 0xcc
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# CHECK: r17 |= lsr(r21, r31)
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0x91 0xdf 0x15 0xcc
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# CHECK: r17 |= asl(r21, r31)
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0xd1 0xdf 0x15 0xcc
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# CHECK: r17 |= lsl(r21, r31)
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0x11 0xdf 0x55 0xcc
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# CHECK: r17 &= asr(r21, r31)
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0x51 0xdf 0x55 0xcc
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# CHECK: r17 &= lsr(r21, r31)
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0x91 0xdf 0x55 0xcc
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# CHECK: r17 &= asl(r21, r31)
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0xd1 0xdf 0x55 0xcc
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# CHECK: r17 &= lsl(r21, r31)
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