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[DAGCombine] Replace getIntPtrConstant() with getVectorIdxTy().

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- Prefer `getVectorIdxTy()` as the index operand type for
  `EXTRACT_SUBVECTOR` as targets expect different types by overloading
  `getVectorIdxTy()`.
This commit is contained in:
Michael Liao 2020-01-14 16:30:52 -05:00
parent efaddf0ae6
commit b78c93696a
2 changed files with 42 additions and 1 deletions
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3
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -18606,7 +18606,8 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
"Trying to extract from >1 concat operand?");
assert(NewExtIdx % ExtNumElts == 0 &&
"Extract index is not a multiple of the input vector length.");
SDValue NewIndexC = DAG.getIntPtrConstant(NewExtIdx, DL);
MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
SDValue NewIndexC = DAG.getConstant(NewExtIdx, DL, IdxTy);
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NVT,
V.getOperand(ConcatOpIdx), NewIndexC);
}

40
test/CodeGen/AMDGPU/extract-subvector.ll Normal file
View File

@ -0,0 +1,40 @@
; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs -o - %s | FileCheck %s
; CHECK-LABEL: foo
; CHECK: buffer_load_ushort
; CHECK: buffer_load_ushort
; CHECK: buffer_load_ushort
; CHECK: buffer_load_ushort
; CHECK: buffer_load_ushort
; CHECK: buffer_load_ushort
; CHECK: buffer_load_ushort
; CHECK: buffer_load_ushort
; CHECK: buffer_load_ushort
; CHECK: buffer_load_ushort
; CHECK: buffer_load_ushort
; CHECK: buffer_load_ushort
; CHECK: buffer_load_ushort
; CHECK: buffer_load_ushort
; CHECK: buffer_load_ushort
; CHECK: buffer_load_ushort
; CHECK: v_bfe_i32
; CHECK: v_bfe_i32
define <2 x i16> @foo(<8 x i16> addrspace(1) * %p0, <8 x i16> addrspace(1) * %p1) {
br i1 undef, label %T, label %F
T:
%t = load volatile <8 x i16>, <8 x i16> addrspace(1) * %p0
br label %exit
F:
%f = load volatile <8 x i16>, <8 x i16> addrspace(1) * %p1
br label %exit
exit:
%m = phi <8 x i16> [ %t, %T ], [ %f, %F ]
%v2 = shufflevector <8 x i16> %m, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
%b2 = icmp sgt <2 x i16> %v2, <i16 -1, i16 -1>
%r2 = select <2 x i1> %b2, <2 x i16> <i16 -32768, i16 -32768>, <2 x i16> <i16 -1, i16 -1>
ret <2 x i16> %r2
}