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[ModuloSchedule] removeBranch() *before* creating the trip count condition

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The Hexagon code assumes there's no existing terminator when inserting its
trip count condition check.

This causes swp-stages5.ll to break. The generated code looks good to me,
it is likely a permutation. I have disabled the new codegen path to keep
everything green and will investigate along with the other 3-4 tests
that have different codegen.

Fixes expensive-checks build.

llvm-svn: 373629
This commit is contained in:
James Molloy 2019-10-03 17:10:32 +00:00
parent 80f09c72f7
commit b8695c33a2
2 changed files with 2 additions and 3 deletions
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3
lib/CodeGen/ModuloSchedule.cpp
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@ -1772,12 +1772,12 @@ void PeelingModuloScheduleExpander::fixupBranches() {
MachineBasicBlock *Fallthrough = *Prolog->succ_begin(); MachineBasicBlock *Fallthrough = *Prolog->succ_begin();
MachineBasicBlock *Epilog = *EI; MachineBasicBlock *Epilog = *EI;
SmallVector<MachineOperand, 4> Cond; SmallVector<MachineOperand, 4> Cond;
TII->removeBranch(*Prolog);
Optional<bool> StaticallyGreater = Optional<bool> StaticallyGreater =
Info->createTripCountGreaterCondition(TC, *Prolog, Cond); Info->createTripCountGreaterCondition(TC, *Prolog, Cond);
if (!StaticallyGreater.hasValue()) { if (!StaticallyGreater.hasValue()) {
LLVM_DEBUG(dbgs() << "Dynamic: TC > " << TC << "\n"); LLVM_DEBUG(dbgs() << "Dynamic: TC > " << TC << "\n");
// Dynamically branch based on Cond. // Dynamically branch based on Cond.
TII->removeBranch(*Prolog);
TII->insertBranch(*Prolog, Epilog, Fallthrough, Cond, DebugLoc()); TII->insertBranch(*Prolog, Epilog, Fallthrough, Cond, DebugLoc());
} else if (*StaticallyGreater == false) { } else if (*StaticallyGreater == false) {
LLVM_DEBUG(dbgs() << "Static-false: TC > " << TC << "\n"); LLVM_DEBUG(dbgs() << "Static-false: TC > " << TC << "\n");
@ -1788,7 +1788,6 @@ void PeelingModuloScheduleExpander::fixupBranches() {
P.RemoveOperand(2); P.RemoveOperand(2);
P.RemoveOperand(1); P.RemoveOperand(1);
} }
TII->removeBranch(*Prolog);
TII->insertUnconditionalBranch(*Prolog, Epilog, DebugLoc()); TII->insertUnconditionalBranch(*Prolog, Epilog, DebugLoc());
KernelDisposed = true; KernelDisposed = true;
} else { } else {

2
test/CodeGen/Hexagon/swp-stages5.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner -pipeliner-max-stages=2 -hexagon-bit=0 < %s -pipeliner-experimental-cg=true | FileCheck %s ; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner -pipeliner-max-stages=2 -hexagon-bit=0 < %s | FileCheck %s
; Very similar to swp-stages4.ll, but the pipelined schedule is a little ; Very similar to swp-stages4.ll, but the pipelined schedule is a little
; different. ; different.