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Pattern match bitfield insert, which helps shift long by immediate, among
other things. llvm-svn: 21127
This commit is contained in:
Nate Begeman
parent
6c5e4c3bb1
commit
b890f32ac9
@ -489,6 +489,7 @@ public:
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unsigned getGlobalBaseReg();
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unsigned getConstDouble(double floatVal, unsigned Result);
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bool SelectBitfieldInsert(SDOperand OR, unsigned Result);
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unsigned SelectSetCR0(SDOperand CC);
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unsigned SelectExpr(SDOperand N);
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unsigned SelectExprFP(SDOperand N, unsigned Result);
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@ -510,6 +511,61 @@ static unsigned ExactLog2(unsigned Val) {
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return Count;
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}
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// IsRunOfOnes - returns true if Val consists of one contiguous run of 1's with
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// any number of 0's on either side. the 1's are allowed to wrap from LSB to
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// MSB. so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
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// not, since all 1's are not contiguous.
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static bool IsRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
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bool isRun = true;
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MB = 0;
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ME = 0;
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// look for first set bit
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int i = 0;
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for (; i < 32; i++) {
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if ((Val & (1 << (31 - i))) != 0) {
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MB = i;
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ME = i;
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break;
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}
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}
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// look for last set bit
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for (; i < 32; i++) {
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if ((Val & (1 << (31 - i))) == 0)
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break;
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ME = i;
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}
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// look for next set bit
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for (; i < 32; i++) {
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if ((Val & (1 << (31 - i))) != 0)
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break;
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}
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// if we exhausted all the bits, we found a match at this point for 0*1*0*
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if (i == 32)
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return true;
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// since we just encountered more 1's, if it doesn't wrap around to the
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// most significant bit of the word, then we did not find a match to 1*0*1* so
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// exit.
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if (MB != 0)
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return false;
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// look for last set bit
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for (MB = i; i < 32; i++) {
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if ((Val & (1 << (31 - i))) == 0)
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break;
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}
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// if we exhausted all the bits, then we found a match for 1*0*1*, otherwise,
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// the value is not a run of ones.
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if (i == 32)
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return true;
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return false;
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}
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/// getImmediateForOpcode - This method returns a value indicating whether
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/// the ConstantSDNode N can be used as an immediate to Opcode. The return
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/// values are either 0, 1 or 2. 0 indicates that either N is not a
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@ -769,6 +825,78 @@ unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
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return Result;
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}
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/// SelectBitfieldInsert - turn an or of two masked values into
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/// the rotate left word immediate then mask insert (rlwimi) instruction.
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/// Returns true on success, false if the caller still needs to select OR.
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///
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/// Patterns matched:
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/// 1. or shl, and 5. or and, and
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/// 2. or and, shl 6. or shl, shr
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/// 3. or shr, and 7. or shr, shl
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/// 4. or and, shr
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bool ISel::SelectBitfieldInsert(SDOperand OR, unsigned Result) {
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unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, Amount = 0;
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unsigned Op0Opc = OR.getOperand(0).getOpcode();
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unsigned Op1Opc = OR.getOperand(1).getOpcode();
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// Verify that we have the correct opcodes
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if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
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return false;
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if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
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return false;
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// Generate Mask value for Target
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if (ConstantSDNode *CN =
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dyn_cast<ConstantSDNode>(OR.getOperand(0).getOperand(1).Val)) {
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switch(Op0Opc) {
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case ISD::SHL: TgtMask <<= (unsigned)CN->getValue(); break;
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case ISD::SRL: TgtMask >>= (unsigned)CN->getValue(); break;
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case ISD::AND: TgtMask &= (unsigned)CN->getValue(); break;
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}
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} else {
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return false;
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}
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// Generate Mask value for Insert
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if (ConstantSDNode *CN =
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dyn_cast<ConstantSDNode>(OR.getOperand(1).getOperand(1).Val)) {
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switch(Op1Opc) {
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case ISD::SHL:
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Amount = CN->getValue();
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InsMask <<= Amount;
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break;
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case ISD::SRL:
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Amount = CN->getValue();
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InsMask >>= Amount;
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Amount = 32-Amount;
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break;
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case ISD::AND:
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InsMask &= (unsigned)CN->getValue();
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break;
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}
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} else {
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return false;
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}
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// Verify that the Target mask and Insert mask together form a full word mask
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// and that the Insert mask is a run of set bits (which implies both are runs
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// of set bits). Given that, Select the arguments and generate the rlwimi
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// instruction.
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unsigned MB, ME;
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if (((TgtMask ^ InsMask) == 0xFFFFFFFF) && IsRunOfOnes(InsMask, MB, ME)) {
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unsigned Tmp1, Tmp2;
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if (Op0Opc == ISD::AND)
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Tmp1 = SelectExpr(OR.getOperand(0).getOperand(0));
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else
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Tmp1 = SelectExpr(OR.getOperand(0));
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Tmp2 = SelectExpr(OR.getOperand(1).getOperand(0));
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BuildMI(BB, PPC::RLWIMI, 5, Result).addReg(Tmp1).addReg(Tmp2)
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.addImm(Amount).addImm(MB).addImm(ME);
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return true;
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}
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return false;
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}
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unsigned ISel::SelectSetCR0(SDOperand CC) {
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unsigned Opc, Tmp1, Tmp2;
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static const unsigned CompareOpcodes[] =
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@ -1476,31 +1604,40 @@ unsigned ISel::SelectExpr(SDOperand N) {
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return Result;
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case ISD::AND:
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Tmp1 = SelectExpr(N.getOperand(0));
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// FIXME: should add check in getImmediateForOpcode to return a value
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// indicating the immediate is a run of set bits so we can emit a bitfield
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// clear with RLWINM instead.
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switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
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default: assert(0 && "unhandled result code");
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case 0: // No immediate
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, PPC::AND, 2, Result).addReg(Tmp1).addReg(Tmp2);
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break;
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case 1: // Low immediate
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BuildMI(BB, PPC::ANDIo, 2, Result).addReg(Tmp1).addImm(Tmp2);
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break;
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case 2: // Shifted immediate
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BuildMI(BB, PPC::ANDISo, 2, Result).addReg(Tmp1).addImm(Tmp2);
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break;
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}
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return Result;
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case ISD::OR:
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if (SelectBitfieldInsert(N, Result))
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return Result;
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Tmp1 = SelectExpr(N.getOperand(0));
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switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
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default: assert(0 && "unhandled result code");
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case 0: // No immediate
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Tmp2 = SelectExpr(N.getOperand(1));
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switch (opcode) {
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case ISD::AND: Opc = PPC::AND; break;
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case ISD::OR: Opc = PPC::OR; break;
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}
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp2);
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break;
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case 1: // Low immediate
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switch (opcode) {
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case ISD::AND: Opc = PPC::ANDIo; break;
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case ISD::OR: Opc = PPC::ORI; break;
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}
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
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BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(Tmp2);
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break;
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case 2: // Shifted immediate
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switch (opcode) {
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case ISD::AND: Opc = PPC::ANDISo; break;
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case ISD::OR: Opc = PPC::ORIS; break;
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}
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
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BuildMI(BB, PPC::ORIS, 2, Result).addReg(Tmp1).addImm(Tmp2);
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break;
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}
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return Result;
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