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[mips] Add instruction itinerary classes for mult, seb and slt instructions.

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llvm-svn: 186222
This commit is contained in:
Akira Hatanaka 2013-07-12 22:43:20 +00:00
parent c4d489b5ee
commit b94a7de0c8
3 changed files with 16 additions and 13 deletions
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8
lib/Target/Mips/Mips64InstrInfo.td
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@ -181,14 +181,14 @@ def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
let DecoderNamespace = "Mips64" in {
/// Multiply and Divide Instructions.
def DMULT : Mult<"dmult", IIImul, CPU64RegsOpnd, [HI64, LO64]>,
def DMULT : Mult<"dmult", IIImult, CPU64RegsOpnd, [HI64, LO64]>,
MULT_FM<0, 0x1c>;
def DMULTu : Mult<"dmultu", IIImul, CPU64RegsOpnd, [HI64, LO64]>,
def DMULTu : Mult<"dmultu", IIImult, CPU64RegsOpnd, [HI64, LO64]>,
MULT_FM<0, 0x1d>;
def PseudoDMULT : MultDivPseudo<DMULT, ACRegs128, CPU64RegsOpnd, MipsMult,
IIImul>;
IIImult>;
def PseudoDMULTu : MultDivPseudo<DMULTu, ACRegs128, CPU64RegsOpnd, MipsMultu,
IIImul>;
IIImult>;
def DSDIV : Div<"ddiv", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1e>;
def DUDIV : Div<"ddivu", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1f>;
def PseudoDSDIV : MultDivPseudo<DSDIV, ACRegs128, CPU64RegsOpnd, MipsDivRem,

18
lib/Target/Mips/MipsInstrInfo.td
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@ -403,7 +403,7 @@ class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
// Arithmetic Multiply ADD/SUB
class MArithR<string opstr, bit isComm = 0> :
InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt),
!strconcat(opstr, "\t$rs, $rt"), [], IIImul, FrmR> {
!strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR> {
let Defs = [HI, LO];
let Uses = [HI, LO];
let isCommutable = isComm;
@ -560,14 +560,14 @@ class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> :
InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt),
!strconcat(opstr, "\t$rd, $rs, $rt"),
[(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))],
IIAlu, FrmR, opstr>;
IIslt, FrmR, opstr>;
class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
RegisterClass RC>:
InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16),
!strconcat(opstr, "\t$rt, $rs, $imm16"),
[(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))],
IIAlu, FrmI, opstr>;
IIslt, FrmI, opstr>;
// Jump
class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
@ -694,7 +694,7 @@ class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
(ins CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin),
[(set ACRegs:$ac,
(OpNode CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin))],
IIImul>,
IIImult>,
PseudoInstExpansion<(RealInst CPURegsOpnd:$rs, CPURegsOpnd:$rt)> {
string Constraints = "$acin = $ac";
}
@ -741,7 +741,7 @@ class CountLeading1<string opstr, RegisterOperand RO>:
// Sign Extend in Register.
class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> :
InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"),
[(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> {
[(set RC:$rd, (sext_inreg RC:$rt, vt))], IIseb, FrmR> {
let Predicates = [HasSEInReg, HasStdEnc];
}
@ -1015,12 +1015,12 @@ let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
}
/// Multiply and Divide Instructions.
def MULT : MMRel, Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>,
def MULT : MMRel, Mult<"mult", IIImult, CPURegsOpnd, [HI, LO]>,
MULT_FM<0, 0x18>;
def MULTu : MMRel, Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>,
def MULTu : MMRel, Mult<"multu", IIImult, CPURegsOpnd, [HI, LO]>,
MULT_FM<0, 0x19>;
def PseudoMULT : MultDivPseudo<MULT, ACRegs, CPURegsOpnd, MipsMult, IIImul>;
def PseudoMULTu : MultDivPseudo<MULTu, ACRegs, CPURegsOpnd, MipsMultu, IIImul>;
def PseudoMULT : MultDivPseudo<MULT, ACRegs, CPURegsOpnd, MipsMult, IIImult>;
def PseudoMULTu : MultDivPseudo<MULTu, ACRegs, CPURegsOpnd, MipsMultu, IIImult>;
def SDIV : Div<"div", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1a>;
def UDIV : Div<"divu", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1b>;
def PseudoSDIV : MultDivPseudo<SDIV, ACRegs, CPURegsOpnd, MipsDivRem, IIIdiv,

3
lib/Target/Mips/MipsSchedule.td
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@ -23,7 +23,10 @@ def IIXfer : InstrItinClass;
def IIBranch : InstrItinClass;
def IIHiLo : InstrItinClass;
def IIImul : InstrItinClass;
def IIImult : InstrItinClass;
def IIIdiv : InstrItinClass;
def IIseb : InstrItinClass;
def IIslt : InstrItinClass;
def IIFcvt : InstrItinClass;
def IIFmove : InstrItinClass;
def IIFcmp : InstrItinClass;