RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-04-03 16:21:41 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[mips] Test case for r182042. Add comment.

Browse Source 
llvm-svn: 182044
This commit is contained in:
Akira Hatanaka 2013-05-16 19:57:23 +00:00
parent fe7cc5cbd7
commit ba455f200e
2 changed files with 60 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/Mips/MipsSEInstrInfo.h
View File

@ -83,9 +83,21 @@ private:
void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned Opc) const; unsigned Opc) const;
/// Expand pseudo Int-to-FP conversion instructions.
///
/// For example, the following pseudo instruction
/// PseudoCVT_D32_W D2, A5
/// gets expanded into these two instructions:
/// MTC1 F4, A5
/// CVT_D32_W D2, F4
///
/// We do this expansion post-RA to avoid inserting a floating point copy
/// instruction between MTC1 and CVT_D32_W.
void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned CvtOpc, unsigned MovOpc, bool DstIsLarger, unsigned CvtOpc, unsigned MovOpc, bool DstIsLarger,
bool SrcIsLarger, bool IsI64) const; bool SrcIsLarger, bool IsI64) const;
void expandExtractElementF64(MachineBasicBlock &MBB, void expandExtractElementF64(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const; MachineBasicBlock::iterator I) const;
void expandBuildPairF64(MachineBasicBlock &MBB, void expandBuildPairF64(MachineBasicBlock &MBB,

48
test/CodeGen/Mips/int-to-float-conversion.ll Normal file
View File

@ -0,0 +1,48 @@
; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
@i3 = common global i32* null, align 4
; 32: test_float_int_:
; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
; 32: cvt.s.w $f{{[0-9]+}}, $f[[R0]]
define float @test_float_int_(i32 %a) {
entry:
%conv = sitofp i32 %a to float
ret float %conv
}
; 32: test_double_int_:
; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
; 32: cvt.d.w $f{{[0-9]+}}, $f[[R0]]
; 64: test_double_int_:
; 64: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
; 64: cvt.d.w $f{{[0-9]+}}, $f[[R0]]
define double @test_double_int_(i32 %a) {
entry:
%conv = sitofp i32 %a to double
ret double %conv
}
; 64: test_float_LL_:
; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
; 64: cvt.s.l $f{{[0-9]+}}, $f[[R0]]
define float @test_float_LL_(i64 %a) {
entry:
%conv = sitofp i64 %a to float
ret float %conv
}
; 64: test_double_LL_:
; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
; 64: cvt.d.l $f{{[0-9]+}}, $f[[R0]]
define double @test_double_LL_(i64 %a) {
entry:
%conv = sitofp i64 %a to double
ret double %conv
}