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Fix (movhps load) lowering / pattern to match more cases. rdar://10050549
llvm-svn: 138848
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928959bc52
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@ -6236,8 +6236,11 @@ SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
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if (HasSSE2 && VT == MVT::v2f64)
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return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
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// v4f32 or v4i32
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return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
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// v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
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return DAG.getNode(ISD::BITCAST, dl, VT,
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getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
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DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
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DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
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}
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static
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@ -691,11 +691,12 @@ let Predicates = [HasSSE1] in {
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// MOVHPS patterns
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def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
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(MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
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def : Pat<(X86Movlhps VR128:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
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(MOVHPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(X86Movlhps VR128:$src1,
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(bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
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(bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
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(MOVHPSrm VR128:$src1, addr:$src2)>;
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// MOVLHPS patterns
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@ -24,3 +24,22 @@ define <2 x i64> @hdi(<2 x i64> %p) nounwind optsize ssp {
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ret <2 x i64> %shuffle
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}
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; rdar://10050549
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%struct.Float2 = type { float, float }
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define <4 x float> @loadhpi(%struct.Float2* %vPtr, <4 x float> %vecin1) nounwind readonly ssp {
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entry:
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; CHECK: loadhpi
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; CHECK-NOT: movq
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; CHECK: movhps (
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%tmp1 = bitcast %struct.Float2* %vPtr to <1 x i64>*
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%addptr7 = getelementptr inbounds <1 x i64>* %tmp1, i64 0
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%tmp2 = bitcast <1 x i64>* %addptr7 to float*
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%tmp3 = load float* %tmp2, align 4
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%vec = insertelement <4 x float> undef, float %tmp3, i32 0
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%addptr.i12 = getelementptr inbounds float* %tmp2, i64 1
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%tmp4 = load float* %addptr.i12, align 4
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%vecin2 = insertelement <4 x float> %vec, float %tmp4, i32 1
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%shuffle = shufflevector <4 x float> %vecin1, <4 x float> %vecin2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
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ret <4 x float> %shuffle
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}
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