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[GlobalISel][AArch64] Select llvm.bswap* for non-vector types
This teaches the IRTranslator to emit G_BSWAP when it runs into Intrinsic::bswap. This allows us to select G_BSWAP for non-vector types in AArch64. Add a select-bswap.mir test, and add global isel checks to a couple existing tests in test/CodeGen/AArch64. This doesn't handle every bswap case, since some of these rely on known bits stuff. This just lets us handle the naive case. Differential Revision: https://reviews.llvm.org/D58081 llvm-svn: 353861
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@ -794,6 +794,8 @@ IRTranslator::getSimpleUnaryIntrinsicOpcode(Intrinsic::ID ID) {
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switch (ID) {
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default:
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break;
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case Intrinsic::bswap:
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return TargetOpcode::G_BSWAP;
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case Intrinsic::ceil:
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return TargetOpcode::G_FCEIL;
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case Intrinsic::cos:
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38
lib/Target/AArch64/select-bswap.mir
Normal file
38
lib/Target/AArch64/select-bswap.mir
Normal file
@ -0,0 +1,38 @@
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# RUN: llc -verify-machineinstrs -mtriple aarch64--- \
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# RUN: -run-pass=instruction-select -mattr=+fullfp16 -global-isel %s -o - \
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# RUN: | FileCheck %s
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...
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---
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name: bswap_s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: bswap_s32
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[REVWr:%[0-9]+]]:gpr32 = REVWr [[COPY]]
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; CHECK: $w0 = COPY [[REVWr]]
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liveins: $s0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = G_BSWAP %0
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$w0 = COPY %1(s32)
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...
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---
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name: bswap_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: bswap_s64
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[REVXr:%[0-9]+]]:gpr64 = REVXr [[COPY]]
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; CHECK: $x0 = COPY [[REVXr]]
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liveins: $x0
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%0:gpr(s64) = COPY $d0
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%1:gpr(s64) = G_BSWAP %0
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$x0 = COPY %1(s64)
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...
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@ -1,21 +1,32 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=apple | FileCheck %s
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; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=aarch64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=FALLBACK,GISEL
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; FALLBACK-NOT: remark{{.*}}test_rev_w
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define i32 @test_rev_w(i32 %a) nounwind {
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; CHECK-LABEL: test_rev_w:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rev w0, w0
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; CHECK-NEXT: ret
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; GISEL-LABEL: test_rev_w:
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; GISEL: // %bb.0: // %entry
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; GISEL-NEXT: rev w0, w0
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; GISEL-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.bswap.i32(i32 %a)
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ret i32 %0
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}
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; FALLBACK-NOT: remark{{.*}}test_rev_x
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define i64 @test_rev_x(i64 %a) nounwind {
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; CHECK-LABEL: test_rev_x:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rev x0, x0
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; CHECK-NEXT: ret
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; GISEL-LABEL: test_rev_x:
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; GISEL: // %bb.0: // %entry
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; GISEL-NEXT: rev x0, x0
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; GISEL-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.bswap.i64(i64 %a)
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ret i64 %0
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@ -1,22 +1,29 @@
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; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
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; RUN: llc -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefixes=FALLBACK,GISEL
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@var32 = global i32 0
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@var64 = global i64 0
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; FALLBACK-NOT: remark{{.*}}rev_i32
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define void @rev_i32() {
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; CHECK-LABEL: rev_i32:
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; GISEL-LABEL: rev_i32:
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%val0_tmp = load i32, i32* @var32
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%val1_tmp = call i32 @llvm.bswap.i32(i32 %val0_tmp)
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; CHECK: rev {{w[0-9]+}}, {{w[0-9]+}}
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; GISEL: rev {{w[0-9]+}}, {{w[0-9]+}}
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store volatile i32 %val1_tmp, i32* @var32
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ret void
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}
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; FALLBACK-NOT: remark{{.*}}rev_i64
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define void @rev_i64() {
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; CHECK-LABEL: rev_i64:
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; GISEL-LABEL: rev_i64:
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%val0_tmp = load i64, i64* @var64
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%val1_tmp = call i64 @llvm.bswap.i64(i64 %val0_tmp)
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; CHECK: rev {{x[0-9]+}}, {{x[0-9]+}}
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; GISEL: rev {{x[0-9]+}}, {{x[0-9]+}}
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store volatile i64 %val1_tmp, i64* @var64
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ret void
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}
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@ -149,4 +156,3 @@ declare i32 @llvm.cttz.i32 (i32, i1)
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declare i64 @llvm.cttz.i64 (i64, i1)
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declare i32 @llvm.ctpop.i32 (i32)
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declare i64 @llvm.ctpop.i64 (i64)
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