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[Hexagon] Use S2_lsr_i_r instead of S2_extractu to obtain upper halfword

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llvm-svn: 257815
This commit is contained in:
Krzysztof Parzyszek 2016-01-14 21:59:22 +00:00
parent 47170eaf07
commit bccfe64a1e
2 changed files with 15 additions and 3 deletions
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5
lib/Target/Hexagon/HexagonBitSimplify.cpp
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@ -1966,11 +1966,10 @@ bool BitSimplification::genExtractHalf(MachineInstr *MI,
NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
BuildMI(B, At, DL, HII.get(Hexagon::A2_zxth), NewR)
.addReg(L.Reg, 0, L.Sub);
} else if (!L.Low && Opc != Hexagon::S2_extractu) {
} else if (!L.Low && Opc != Hexagon::S2_lsr_i_r) {
NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
BuildMI(B, MI, DL, HII.get(Hexagon::S2_extractu), NewR)
BuildMI(B, MI, DL, HII.get(Hexagon::S2_lsr_i_r), NewR)
.addReg(L.Reg, 0, L.Sub)
.addImm(16)
.addImm(16);
}
if (NewR == 0)

13
test/CodeGen/Hexagon/bit-extractu-half.ll Normal file
View File

@ -0,0 +1,13 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Pick lsr (in bit-simplification) for extracting high halfword.
; CHECK: lsr{{.*}}#16
define i32 @foo(i32 %x) #0 {
%a = call i32 @llvm.hexagon.S2.extractu(i32 %x, i32 16, i32 16)
ret i32 %a
}
declare i32 @llvm.hexagon.S2.extractu(i32, i32, i32) #0
attributes #0 = { nounwind readnone }