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[X86] Give ADC8/16/32/64mi the same scheduling information as ADC8/16/32/64mr and SBB8/16/32/64mi.

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It doesn't make a lot of sense that it would be different.

llvm-svn: 328946
This commit is contained in:
Craig Topper 2018-04-01 21:54:24 +00:00
parent 8f3fa49caf
commit bcef2c5947
4 changed files with 10 additions and 22 deletions
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6
lib/Target/X86/X86SchedBroadwell.td
View File

@ -2014,15 +2014,15 @@ def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,3];
}
def: InstRW<[BWWriteResGroup99], (instregex "ADC(8|16|32|64)mi",
"XCHG(8|16|32|64)rm")>;
def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>;
def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,2,1];
}
def: InstRW<[BWWriteResGroup100], (instregex "ADC(8|16|32|64)mr",
def: InstRW<[BWWriteResGroup100], (instregex "ADC(8|16|32|64)mi",
"ADC(8|16|32|64)mr",
"CMPXCHG(8|16|32|64)rm",
"ROL(8|16|32|64)mCL",
"SAR(8|16|32|64)mCL",

6
lib/Target/X86/X86SchedHaswell.td
View File

@ -2110,15 +2110,15 @@ def HWWriteResGroup68 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,3];
}
def: InstRW<[HWWriteResGroup68], (instregex "ADC(8|16|32|64)mi",
"XCHG(8|16|32|64)rm")>;
def: InstRW<[HWWriteResGroup68], (instregex "XCHG(8|16|32|64)rm")>;
def HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort0156]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,2,1];
}
def: InstRW<[HWWriteResGroup69], (instregex "ADC(8|16|32|64)mr",
def: InstRW<[HWWriteResGroup69], (instregex "ADC(8|16|32|64)mi",
"ADC(8|16|32|64)mr",
"CMPXCHG(8|16|32|64)rm",
"ROL(8|16|32|64)mCL",
"SAR(8|16|32|64)mCL",

10
lib/Target/X86/X86SchedSkylakeClient.td
View File

@ -2076,19 +2076,13 @@ def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",
"SHL(8|16|32|64)mCL",
"SHR(8|16|32|64)mCL")>;
def SKLWriteResGroup118 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,3];
}
def: InstRW<[SKLWriteResGroup118], (instregex "ADC(8|16|32|64)mi")>;
def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,2,1];
}
def: InstRW<[SKLWriteResGroup119], (instregex "ADC(8|16|32|64)mr",
def: InstRW<[SKLWriteResGroup119], (instregex "ADC(8|16|32|64)mi",
"ADC(8|16|32|64)mr",
"CMPXCHG(8|16|32|64)rm",
"SBB(8|16|32|64)mi",
"SBB(8|16|32|64)mr")>;

10
lib/Target/X86/X86SchedSkylakeServer.td
View File

@ -4416,19 +4416,13 @@ def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
"SHL(8|16|32|64)mCL",
"SHR(8|16|32|64)mCL")>;
def SKXWriteResGroup129 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,3];
}
def: InstRW<[SKXWriteResGroup129], (instregex "ADC(8|16|32|64)mi")>;
def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,2,1];
}
def: InstRW<[SKXWriteResGroup130], (instregex "ADC(8|16|32|64)mr",
def: InstRW<[SKXWriteResGroup130], (instregex "ADC(8|16|32|64)mi",
"ADC(8|16|32|64)mr",
"CMPXCHG(8|16|32|64)rm",
"SBB(8|16|32|64)mi",
"SBB(8|16|32|64)mr")>;