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[X86] Add isel pattern for (v8i16 (sext (v8i1))) with DQI and no BWI.

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Our lowering that tries to avoid this sign extend can be defeated by the DAG combine folding it with a truncate.

The pattern needs to extend to an v8i32 then truncate back down to v8i16.

llvm-svn: 342830
This commit is contained in:
Craig Topper 2018-09-23 06:49:48 +00:00
parent 42725f99d0
commit be00efe529
2 changed files with 536 additions and 118 deletions
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5
lib/Target/X86/X86InstrAVX512.td
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@ -9687,6 +9687,11 @@ let Predicates = [HasDQI, NoBWI] in {
(VPMOVDWZrr (v16i32 (VPMOVM2DZrr VK16:$src)))>;
}
let Predicates = [HasDQI, NoBWI, HasVLX] in {
def : Pat<(v8i16 (sext (v8i1 VK8:$src))),
(VPMOVDWZ256rr (v8i32 (VPMOVM2DZ256rr VK8:$src)))>;
}
//===----------------------------------------------------------------------===//
// AVX-512 - COMPRESS and EXPAND
//

649
test/CodeGen/X86/avx512-ext.ll
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