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Fix for the following bug in AVX codegen for double-to-int conversions:

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.	"fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode.
.	Currently for AVX mode for <4xdouble> and <8xdouble>  the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode.
.	Consequently, the conversion produces incorrect numbers.
 
The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode. 
As .fp_to_sint. DAG node operation is used only for lowering of  "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows.
 
The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec). 

llvm-svn: 149056
This commit is contained in:
Victor Umansky 2012-01-26 08:51:39 +00:00
parent 8f8e428400
commit bf35274368
3 changed files with 22 additions and 3 deletions
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4
lib/Target/X86/X86InstrSSE.td
View File

@ -4693,9 +4693,9 @@ def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
(VCVTPD2DQYrr VR256:$src)>;
(VCVTTPD2DQYrr VR256:$src)>;
def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
(VCVTPD2DQYrm addr:$src)>;
(VCVTTPD2DQYrm addr:$src)>;
// Convert Packed DW Integers to Packed Double FP
let Predicates = [HasAVX] in {

2
test/CodeGen/X86/avx-cvt.ll
View File

@ -18,7 +18,7 @@ define <4 x double> @sitofp01(<4 x i32> %a) {
ret <4 x double> %b
}
; CHECK: vcvtpd2dqy %ymm
; CHECK: vcvttpd2dqy %ymm
define <4 x i32> @fptosi01(<4 x double> %a) {
%b = fptosi <4 x double> %a to <4 x i32>
ret <4 x i32> %b

19
test/CodeGen/X86/avx-fp2int.ll Executable file
View File

@ -0,0 +1,19 @@
; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=corei7-avx -mattr=+avx | FileCheck %s
;; Check that FP_TO_SINT and FP_TO_UINT generate convert with truncate
; CHECK: test1:
; CHECK: vcvttpd2dqy
; CHECK: ret
; CHECK: test2:
; CHECK: vcvttpd2dqy
; CHECK: ret
define <4 x i8> @test1(<4 x double> %d) {
%c = fptoui <4 x double> %d to <4 x i8>
ret <4 x i8> %c
}
define <4 x i8> @test2(<4 x double> %d) {
%c = fptosi <4 x double> %d to <4 x i8>
ret <4 x i8> %c
}