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[AArch64] Move comments closer to relevant check. NFC.
llvm-svn: 272430
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@ -1247,10 +1247,6 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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// check for +1/-1. Make sure to check the new instruction offset is
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// actually an immediate and not a symbolic reference destined for
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// a relocation.
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//
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// Pairwise instructions have a 7-bit signed offset field. Single insns
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// have a 12-bit unsigned offset field. To be a valid combine, the
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// final offset must be in range.
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unsigned MIBaseReg = getLdStBaseOp(MI).getReg();
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int MIOffset = getLdStOffsetOp(MI).getImm();
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bool MIIsUnscaled = TII->isUnscaledLdSt(MI);
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@ -1285,8 +1281,10 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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continue;
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}
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} else {
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// If the resultant immediate offset of merging these instructions
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// is out of range for a pairwise instruction, bail and keep looking.
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// Pairwise instructions have a 7-bit signed offset field. Single
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// insns have a 12-bit unsigned offset field. If the resultant
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// immediate offset of merging these instructions is out of range for
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// a pairwise instruction, bail and keep looking.
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if (!inBoundsForPair(IsUnscaled, MinOffset, OffsetStride)) {
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trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
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MemInsns.push_back(MI);
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