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[DAGCombiner] use root SDLoc for all nodes created by logic fold

Browse Source 
If this is not a valid way to assign an SDLoc, then we get this
wrong all over SDAG.

I don't know enough about the SDAG to explain this. IIUC, theoretically,
debug info is not supposed to affect codegen. But here it has clearly
affected 3 different targets, and the x86 change is an actual improvement.

llvm-svn: 348552
This commit is contained in:
Sanjay Patel 2018-12-07 00:01:57 +00:00
parent 2801d1750e
commit c041183d75
4 changed files with 73 additions and 77 deletions
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2
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -3754,7 +3754,7 @@ SDValue DAGCombiner::hoistLogicOpWithSameOpcodeHands(SDNode *N) {
return SDValue();
}
// logic_op (hand_op X), (hand_op Y) --> hand_op (logic_op X, Y)
SDValue Logic = DAG.getNode(LogicOpcode, SDLoc(N0), XVT, X, Y);
SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
AddToWorklist(Logic.getNode());
return DAG.getNode(HandOpcode, DL, VT, Logic);
}

12
test/CodeGen/AArch64/unfold-masked-merge-scalar-variablemask.ll
View File

@ -65,9 +65,9 @@ define i64 @out64(i64 %x, i64 %y, i64 %mask) {
define i8 @in8(i8 %x, i8 %y, i8 %mask) {
; CHECK-LABEL: in8:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, w2
; CHECK-NEXT: bic w9, w1, w2
; CHECK-NEXT: orr w0, w8, w9
; CHECK-NEXT: bic w8, w1, w2
; CHECK-NEXT: and w9, w0, w2
; CHECK-NEXT: orr w0, w9, w8
; CHECK-NEXT: ret
%n0 = xor i8 %x, %y
%n1 = and i8 %n0, %mask
@ -78,9 +78,9 @@ define i8 @in8(i8 %x, i8 %y, i8 %mask) {
define i16 @in16(i16 %x, i16 %y, i16 %mask) {
; CHECK-LABEL: in16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, w2
; CHECK-NEXT: bic w9, w1, w2
; CHECK-NEXT: orr w0, w8, w9
; CHECK-NEXT: bic w8, w1, w2
; CHECK-NEXT: and w9, w0, w2
; CHECK-NEXT: orr w0, w9, w8
; CHECK-NEXT: ret
%n0 = xor i16 %x, %y
%n1 = and i16 %n0, %mask

8
test/CodeGen/PowerPC/setcc-logic.ll
View File

@ -435,9 +435,9 @@ define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) {
define zeroext i1 @and_eq(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i16 zeroext %d) {
; CHECK-LABEL: and_eq:
; CHECK: # %bb.0:
; CHECK-NEXT: xor 5, 5, 6
; CHECK-NEXT: xor 3, 3, 4
; CHECK-NEXT: or 3, 3, 5
; CHECK-NEXT: xor 4, 5, 6
; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: cntlzw 3, 3
; CHECK-NEXT: srwi 3, 3, 5
; CHECK-NEXT: blr
@ -450,9 +450,9 @@ define zeroext i1 @and_eq(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i16 z
define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK-LABEL: or_ne:
; CHECK: # %bb.0:
; CHECK-NEXT: xor 5, 5, 6
; CHECK-NEXT: xor 3, 3, 4
; CHECK-NEXT: or 3, 3, 5
; CHECK-NEXT: xor 4, 5, 6
; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: cntlzw 3, 3
; CHECK-NEXT: srwi 3, 3, 5
; CHECK-NEXT: xori 3, 3, 1

128
test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll
View File

@ -38,8 +38,8 @@ define <2 x i8> @out_v2i8(<2 x i8> %x, <2 x i8> %y, <2 x i8> %mask) nounwind {
; CHECK-BASELINE-LABEL: out_v2i8:
; CHECK-BASELINE: # %bb.0:
; CHECK-BASELINE-NEXT: movl %r8d, %eax
; CHECK-BASELINE-NEXT: andl %r8d, %edi
; CHECK-BASELINE-NEXT: andl %r9d, %esi
; CHECK-BASELINE-NEXT: andl %r8d, %edi
; CHECK-BASELINE-NEXT: notb %al
; CHECK-BASELINE-NEXT: notb %r9b
; CHECK-BASELINE-NEXT: andb %cl, %r9b
@ -53,8 +53,8 @@ define <2 x i8> @out_v2i8(<2 x i8> %x, <2 x i8> %y, <2 x i8> %mask) nounwind {
; CHECK-SSE1-LABEL: out_v2i8:
; CHECK-SSE1: # %bb.0:
; CHECK-SSE1-NEXT: movl %r8d, %eax
; CHECK-SSE1-NEXT: andl %r8d, %edi
; CHECK-SSE1-NEXT: andl %r9d, %esi
; CHECK-SSE1-NEXT: andl %r8d, %edi
; CHECK-SSE1-NEXT: notb %al
; CHECK-SSE1-NEXT: notb %r9b
; CHECK-SSE1-NEXT: andb %cl, %r9b
@ -2587,12 +2587,12 @@ define <2 x i8> @in_v2i8(<2 x i8> %x, <2 x i8> %y, <2 x i8> %mask) nounwind {
; CHECK-BASELINE-LABEL: in_v2i8:
; CHECK-BASELINE: # %bb.0:
; CHECK-BASELINE-NEXT: movl %edi, %eax
; CHECK-BASELINE-NEXT: xorl %ecx, %esi
; CHECK-BASELINE-NEXT: xorl %edx, %eax
; CHECK-BASELINE-NEXT: andl %r8d, %eax
; CHECK-BASELINE-NEXT: xorl %ecx, %esi
; CHECK-BASELINE-NEXT: andl %r9d, %esi
; CHECK-BASELINE-NEXT: xorl %ecx, %esi
; CHECK-BASELINE-NEXT: andl %r8d, %eax
; CHECK-BASELINE-NEXT: xorl %edx, %eax
; CHECK-BASELINE-NEXT: xorl %ecx, %esi
; CHECK-BASELINE-NEXT: # kill: def $al killed $al killed $eax
; CHECK-BASELINE-NEXT: movl %esi, %edx
; CHECK-BASELINE-NEXT: retq
@ -2600,12 +2600,12 @@ define <2 x i8> @in_v2i8(<2 x i8> %x, <2 x i8> %y, <2 x i8> %mask) nounwind {
; CHECK-SSE1-LABEL: in_v2i8:
; CHECK-SSE1: # %bb.0:
; CHECK-SSE1-NEXT: movl %edi, %eax
; CHECK-SSE1-NEXT: xorl %ecx, %esi
; CHECK-SSE1-NEXT: xorl %edx, %eax
; CHECK-SSE1-NEXT: andl %r8d, %eax
; CHECK-SSE1-NEXT: xorl %ecx, %esi
; CHECK-SSE1-NEXT: andl %r9d, %esi
; CHECK-SSE1-NEXT: xorl %ecx, %esi
; CHECK-SSE1-NEXT: andl %r8d, %eax
; CHECK-SSE1-NEXT: xorl %edx, %eax
; CHECK-SSE1-NEXT: xorl %ecx, %esi
; CHECK-SSE1-NEXT: # kill: def $al killed $al killed $eax
; CHECK-SSE1-NEXT: movl %esi, %edx
; CHECK-SSE1-NEXT: retq
@ -2650,10 +2650,10 @@ define <4 x i8> @in_v4i8(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind {
; CHECK-BASELINE-LABEL: in_v4i8:
; CHECK-BASELINE: # %bb.0:
; CHECK-BASELINE-NEXT: movq %rdi, %rax
; CHECK-BASELINE-NEXT: xorl %r9d, %esi
; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %dil
; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r10b
; CHECK-BASELINE-NEXT: movb {{[0-9]+}}(%rsp), %r11b
; CHECK-BASELINE-NEXT: xorl %r9d, %esi
; CHECK-BASELINE-NEXT: xorb %r11b, %dl
; CHECK-BASELINE-NEXT: xorb %r10b, %cl
; CHECK-BASELINE-NEXT: xorb %dil, %r8b
@ -2674,10 +2674,10 @@ define <4 x i8> @in_v4i8(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind {
; CHECK-SSE1-LABEL: in_v4i8:
; CHECK-SSE1: # %bb.0:
; CHECK-SSE1-NEXT: movq %rdi, %rax
; CHECK-SSE1-NEXT: xorl %r9d, %esi
; CHECK-SSE1-NEXT: movb {{[0-9]+}}(%rsp), %dil
; CHECK-SSE1-NEXT: movb {{[0-9]+}}(%rsp), %r10b
; CHECK-SSE1-NEXT: movb {{[0-9]+}}(%rsp), %r11b
; CHECK-SSE1-NEXT: xorl %r9d, %esi
; CHECK-SSE1-NEXT: xorb %r11b, %dl
; CHECK-SSE1-NEXT: xorb %r10b, %cl
; CHECK-SSE1-NEXT: xorb %dil, %r8b
@ -2716,12 +2716,12 @@ define <2 x i16> @in_v2i16(<2 x i16> %x, <2 x i16> %y, <2 x i16> %mask) nounwind
; CHECK-BASELINE-LABEL: in_v2i16:
; CHECK-BASELINE: # %bb.0:
; CHECK-BASELINE-NEXT: movl %edi, %eax
; CHECK-BASELINE-NEXT: xorl %ecx, %esi
; CHECK-BASELINE-NEXT: xorl %edx, %eax
; CHECK-BASELINE-NEXT: andl %r8d, %eax
; CHECK-BASELINE-NEXT: xorl %ecx, %esi
; CHECK-BASELINE-NEXT: andl %r9d, %esi
; CHECK-BASELINE-NEXT: xorl %ecx, %esi
; CHECK-BASELINE-NEXT: andl %r8d, %eax
; CHECK-BASELINE-NEXT: xorl %edx, %eax
; CHECK-BASELINE-NEXT: xorl %ecx, %esi
; CHECK-BASELINE-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-BASELINE-NEXT: movl %esi, %edx
; CHECK-BASELINE-NEXT: retq
@ -2729,12 +2729,12 @@ define <2 x i16> @in_v2i16(<2 x i16> %x, <2 x i16> %y, <2 x i16> %mask) nounwind
; CHECK-SSE1-LABEL: in_v2i16:
; CHECK-SSE1: # %bb.0:
; CHECK-SSE1-NEXT: movl %edi, %eax
; CHECK-SSE1-NEXT: xorl %ecx, %esi
; CHECK-SSE1-NEXT: xorl %edx, %eax
; CHECK-SSE1-NEXT: andl %r8d, %eax
; CHECK-SSE1-NEXT: xorl %ecx, %esi
; CHECK-SSE1-NEXT: andl %r9d, %esi
; CHECK-SSE1-NEXT: xorl %ecx, %esi
; CHECK-SSE1-NEXT: andl %r8d, %eax
; CHECK-SSE1-NEXT: xorl %edx, %eax
; CHECK-SSE1-NEXT: xorl %ecx, %esi
; CHECK-SSE1-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-SSE1-NEXT: movl %esi, %edx
; CHECK-SSE1-NEXT: retq
@ -2915,12 +2915,12 @@ define <4 x i16> @in_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind
; CHECK-BASELINE: # %bb.0:
; CHECK-BASELINE-NEXT: movq %rdi, %rax
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r10d
; CHECK-BASELINE-NEXT: xorl %r10d, %r8d
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r11d
; CHECK-BASELINE-NEXT: xorl %r11d, %ecx
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %edi
; CHECK-BASELINE-NEXT: xorl %edi, %edx
; CHECK-BASELINE-NEXT: xorl %r9d, %esi
; CHECK-BASELINE-NEXT: xorl %edi, %edx
; CHECK-BASELINE-NEXT: xorl %r11d, %ecx
; CHECK-BASELINE-NEXT: xorl %r10d, %r8d
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r8w
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %dx
@ -2939,12 +2939,12 @@ define <4 x i16> @in_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind
; CHECK-SSE1: # %bb.0:
; CHECK-SSE1-NEXT: movq %rdi, %rax
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %r10d
; CHECK-SSE1-NEXT: xorl %r10d, %r8d
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %r11d
; CHECK-SSE1-NEXT: xorl %r11d, %ecx
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %edi
; CHECK-SSE1-NEXT: xorl %edi, %edx
; CHECK-SSE1-NEXT: xorl %r9d, %esi
; CHECK-SSE1-NEXT: xorl %edi, %edx
; CHECK-SSE1-NEXT: xorl %r11d, %ecx
; CHECK-SSE1-NEXT: xorl %r10d, %r8d
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %r8w
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %cx
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %dx
@ -3288,15 +3288,11 @@ define <8 x i16> @in_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) nounwind
; CHECK-BASELINE-LABEL: in_v8i16:
; CHECK-BASELINE: # %bb.0:
; CHECK-BASELINE-NEXT: pushq %rbp
; CHECK-BASELINE-NEXT: pushq %r14
; CHECK-BASELINE-NEXT: pushq %rbx
; CHECK-BASELINE-NEXT: movq %rdi, %rax
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r10d
; CHECK-BASELINE-NEXT: xorl %r10d, %r9d
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r11d
; CHECK-BASELINE-NEXT: xorl %r11d, %r8d
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %edi
; CHECK-BASELINE-NEXT: xorl %edi, %ecx
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx
; CHECK-BASELINE-NEXT: xorl %ebx, %esi
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %si
@ -3305,29 +3301,32 @@ define <8 x i16> @in_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) nounwind
; CHECK-BASELINE-NEXT: xorl %ebx, %edx
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %dx
; CHECK-BASELINE-NEXT: xorl %ebx, %edx
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %r14d
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx
; CHECK-BASELINE-NEXT: xorl %edi, %ecx
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %edi
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r8w
; CHECK-BASELINE-NEXT: xorl %r11d, %r8d
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx
; CHECK-BASELINE-NEXT: xorl %ebx, %ecx
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %cx
; CHECK-BASELINE-NEXT: xorl %ebx, %ecx
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx
; CHECK-BASELINE-NEXT: xorl %ebx, %r8d
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r8w
; CHECK-BASELINE-NEXT: xorl %ebx, %r8d
; CHECK-BASELINE-NEXT: movl {{[0-9]+}}(%rsp), %ebx
; CHECK-BASELINE-NEXT: xorl %ebx, %r9d
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %r9w
; CHECK-BASELINE-NEXT: xorl %r10d, %r9d
; CHECK-BASELINE-NEXT: xorl %ebx, %r9d
; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp
; CHECK-BASELINE-NEXT: xorw %bx, %bp
; CHECK-BASELINE-NEXT: xorw %di, %bp
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bp
; CHECK-BASELINE-NEXT: xorl %ebx, %ebp
; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx
; CHECK-BASELINE-NEXT: xorw %di, %bx
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bx
; CHECK-BASELINE-NEXT: xorl %edi, %ebx
; CHECK-BASELINE-NEXT: xorl %edi, %ebp
; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %edi
; CHECK-BASELINE-NEXT: xorw %r14w, %di
; CHECK-BASELINE-NEXT: xorw %r11w, %di
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %di
; CHECK-BASELINE-NEXT: xorl %r14d, %edi
; CHECK-BASELINE-NEXT: movw %di, 14(%rax)
; CHECK-BASELINE-NEXT: movw %bx, 12(%rax)
; CHECK-BASELINE-NEXT: xorl %r11d, %edi
; CHECK-BASELINE-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx
; CHECK-BASELINE-NEXT: xorw %r10w, %bx
; CHECK-BASELINE-NEXT: andw {{[0-9]+}}(%rsp), %bx
; CHECK-BASELINE-NEXT: xorl %r10d, %ebx
; CHECK-BASELINE-NEXT: movw %bx, 14(%rax)
; CHECK-BASELINE-NEXT: movw %di, 12(%rax)
; CHECK-BASELINE-NEXT: movw %bp, 10(%rax)
; CHECK-BASELINE-NEXT: movw %r9w, 8(%rax)
; CHECK-BASELINE-NEXT: movw %r8w, 6(%rax)
@ -3335,22 +3334,17 @@ define <8 x i16> @in_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) nounwind
; CHECK-BASELINE-NEXT: movw %dx, 2(%rax)
; CHECK-BASELINE-NEXT: movw %si, (%rax)
; CHECK-BASELINE-NEXT: popq %rbx
; CHECK-BASELINE-NEXT: popq %r14
; CHECK-BASELINE-NEXT: popq %rbp
; CHECK-BASELINE-NEXT: retq
;
; CHECK-SSE1-LABEL: in_v8i16:
; CHECK-SSE1: # %bb.0:
; CHECK-SSE1-NEXT: pushq %rbp
; CHECK-SSE1-NEXT: pushq %r14
; CHECK-SSE1-NEXT: pushq %rbx
; CHECK-SSE1-NEXT: movq %rdi, %rax
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %r10d
; CHECK-SSE1-NEXT: xorl %r10d, %r9d
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %r11d
; CHECK-SSE1-NEXT: xorl %r11d, %r8d
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %edi
; CHECK-SSE1-NEXT: xorl %edi, %ecx
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %ebx
; CHECK-SSE1-NEXT: xorl %ebx, %esi
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %si
@ -3359,29 +3353,32 @@ define <8 x i16> @in_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) nounwind
; CHECK-SSE1-NEXT: xorl %ebx, %edx
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %dx
; CHECK-SSE1-NEXT: xorl %ebx, %edx
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %r14d
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %cx
; CHECK-SSE1-NEXT: xorl %edi, %ecx
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %edi
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %r8w
; CHECK-SSE1-NEXT: xorl %r11d, %r8d
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %ebx
; CHECK-SSE1-NEXT: xorl %ebx, %ecx
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %cx
; CHECK-SSE1-NEXT: xorl %ebx, %ecx
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %ebx
; CHECK-SSE1-NEXT: xorl %ebx, %r8d
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %r8w
; CHECK-SSE1-NEXT: xorl %ebx, %r8d
; CHECK-SSE1-NEXT: movl {{[0-9]+}}(%rsp), %ebx
; CHECK-SSE1-NEXT: xorl %ebx, %r9d
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %r9w
; CHECK-SSE1-NEXT: xorl %r10d, %r9d
; CHECK-SSE1-NEXT: xorl %ebx, %r9d
; CHECK-SSE1-NEXT: movzwl {{[0-9]+}}(%rsp), %ebp
; CHECK-SSE1-NEXT: xorw %bx, %bp
; CHECK-SSE1-NEXT: xorw %di, %bp
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %bp
; CHECK-SSE1-NEXT: xorl %ebx, %ebp
; CHECK-SSE1-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx
; CHECK-SSE1-NEXT: xorw %di, %bx
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %bx
; CHECK-SSE1-NEXT: xorl %edi, %ebx
; CHECK-SSE1-NEXT: xorl %edi, %ebp
; CHECK-SSE1-NEXT: movzwl {{[0-9]+}}(%rsp), %edi
; CHECK-SSE1-NEXT: xorw %r14w, %di
; CHECK-SSE1-NEXT: xorw %r11w, %di
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %di
; CHECK-SSE1-NEXT: xorl %r14d, %edi
; CHECK-SSE1-NEXT: movw %di, 14(%rax)
; CHECK-SSE1-NEXT: movw %bx, 12(%rax)
; CHECK-SSE1-NEXT: xorl %r11d, %edi
; CHECK-SSE1-NEXT: movzwl {{[0-9]+}}(%rsp), %ebx
; CHECK-SSE1-NEXT: xorw %r10w, %bx
; CHECK-SSE1-NEXT: andw {{[0-9]+}}(%rsp), %bx
; CHECK-SSE1-NEXT: xorl %r10d, %ebx
; CHECK-SSE1-NEXT: movw %bx, 14(%rax)
; CHECK-SSE1-NEXT: movw %di, 12(%rax)
; CHECK-SSE1-NEXT: movw %bp, 10(%rax)
; CHECK-SSE1-NEXT: movw %r9w, 8(%rax)
; CHECK-SSE1-NEXT: movw %r8w, 6(%rax)
@ -3389,7 +3386,6 @@ define <8 x i16> @in_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) nounwind
; CHECK-SSE1-NEXT: movw %dx, 2(%rax)
; CHECK-SSE1-NEXT: movw %si, (%rax)
; CHECK-SSE1-NEXT: popq %rbx
; CHECK-SSE1-NEXT: popq %r14
; CHECK-SSE1-NEXT: popq %rbp
; CHECK-SSE1-NEXT: retq
;