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Shrink a BitVector that didn't mean to store bits for all physical registers.
llvm-svn: 123108
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@ -1016,8 +1016,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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<< MF.getFunction()->getName() << '\n');
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// ReMatRegs - Keep track of the registers whose def's are remat'ed.
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BitVector ReMatRegs;
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ReMatRegs.resize(MRI->getLastVirtReg()+1);
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BitVector ReMatRegs(MRI->getNumVirtRegs());
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typedef DenseMap<unsigned, SmallVector<std::pair<unsigned, unsigned>, 4> >
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TiedOperandMap;
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@ -1146,7 +1145,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(dbgs() << "2addr: REMATTING : " << *DefMI << "\n");
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unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg();
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TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI);
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ReMatRegs.set(regB);
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ReMatRegs.set(TargetRegisterInfo::virtReg2Index(regB));
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++NumReMats;
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} else {
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BuildMI(*mbbi, mi, mi->getDebugLoc(), TII->get(TargetOpcode::COPY),
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@ -1232,13 +1231,12 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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}
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// Some remat'ed instructions are dead.
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int VReg = ReMatRegs.find_first();
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while (VReg != -1) {
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for (int i = ReMatRegs.find_first(); i != -1; i = ReMatRegs.find_next(i)) {
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unsigned VReg = TargetRegisterInfo::index2VirtReg(i);
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if (MRI->use_nodbg_empty(VReg)) {
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MachineInstr *DefMI = MRI->getVRegDef(VReg);
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DefMI->eraseFromParent();
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}
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VReg = ReMatRegs.find_next(VReg);
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}
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// Eliminate REG_SEQUENCE instructions. Their whole purpose was to preseve
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