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Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff for
it. I.e., it was always an immediate value. llvm-svn: 121932
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@ -237,9 +237,6 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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// 'off by 4' is implicitly handled by the half-word ordering of the
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// Thumb encoding, so we only need to adjust by 2 here.
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return ((Value - 2) >> 2) & 0xff;
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case ARM::fixup_arm_thumb_ldst:
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// Offset by 4.
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return ((Value - 4) & 0x1f) << 6;
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case ARM::fixup_arm_thumb_cb: {
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// Offset by 4 and don't encode the lower bit, which is always 0.
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uint32_t Binary = (Value - 4) >> 1;
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@ -368,7 +365,6 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
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case ARM::fixup_arm_thumb_br:
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case ARM::fixup_arm_thumb_cb:
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case ARM::fixup_arm_thumb_ldst:
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return 2;
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case ARM::fixup_arm_ldst_pcrel_12:
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@ -65,9 +65,6 @@ enum Fixups {
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// fixup_arm_thumb_cp - Fixup for Thumb load/store from constant pool instrs.
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fixup_arm_thumb_cp,
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// fixup_arm_thumb_ldst - Fixup for Thumb load/store instrs.
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fixup_arm_thumb_ldst,
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// fixup_arm_thumb_bcc - Fixup for Thumb conditional branching instructions.
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fixup_arm_thumb_bcc,
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@ -68,7 +68,6 @@ public:
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{ "fixup_arm_thumb_blx", 7, 21, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_cp", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_ldst", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_bcc", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_movt_hi16", 0, 16, 0 },
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{ "fixup_arm_movw_lo16", 0, 16, 0 },
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@ -824,16 +823,7 @@ getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
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const MCOperand &MO = MI.getOperand(OpIdx);
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const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
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unsigned Rn = getARMRegisterNumbering(MO.getReg());
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unsigned Imm5 = 0;
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if (MO1.isExpr()) {
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const MCExpr *Expr = MO.getExpr();
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MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_thumb_ldst);
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Fixups.push_back(MCFixup::Create(0, Expr, Kind));
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} else {
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Imm5 = MO1.getImm();
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}
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unsigned Imm5 = Imm5 = MO1.getImm();
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return ((Imm5 & 0x1f) << 3) | Rn;
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}
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