RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-04-01 07:11:45 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[mips][microMIPS] Implement PRECR.QB.PH, PRECR_SRA[_R].PH.W, PRECRQ.PH.W, PRECRQ.QB.PH, PRECRQU_S.QB.PH and PRECRQ_RS.PH.W instructions

Browse Source 
Differential Revision: http://reviews.llvm.org/D14605

llvm-svn: 254291
This commit is contained in:
Zlatko Buljan 2015-11-30 08:37:38 +00:00
parent c1aa433aed
commit c26ad2415e
7 changed files with 63 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/Mips/MicroMipsDSPInstrFormats.td
View File

@ -141,3 +141,15 @@ class POOL32A_1RIMM5AC_FMT<string opstr, bits<8> funct> : MMDSPInst<opstr> {
let Inst{13-6} = funct;
let Inst{5-0} = 0b111100;
}
class POOL32A_2RSA5_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
bits<5> rt;
bits<5> rs;
bits<5> sa;
let Inst{31-26} = 0b000000;
let Inst{25-21} = rt;
let Inst{20-16} = rs;
let Inst{15-11} = sa;
let Inst{10-0} = op;
}

20
lib/Target/Mips/MicroMipsDSPInstrInfo.td
View File

@ -120,6 +120,16 @@ class MULQ_RS_PH_MM_ENC : POOL32A_3RB0_FMT<"mulq_rs.ph", 0b0100010101>;
class MULQ_RS_W_MMR2_ENC : POOL32A_3RB0_FMT<"mulq_rs.w", 0b0110010101>;
class MULQ_S_PH_MMR2_ENC : POOL32A_3RB0_FMT<"mulq_s.ph", 0b0101010101>;
class MULQ_S_W_MMR2_ENC : POOL32A_3RB0_FMT<"mulq_s.w", 0b0111010101>;
class PRECR_QB_PH_MMR2_ENC : POOL32A_3RB0_FMT<"precr.qb.ph", 0b0001101101>;
class PRECR_SRA_PH_W_MMR2_ENC
: POOL32A_2RSA5_FMT<"precr_sra.ph.w", 0b01111001101>;
class PRECR_SRA_R_PH_W_MMR2_ENC
: POOL32A_2RSA5_FMT<"precr_sra_r.ph.w", 0b11111001101>;
class PRECRQ_PH_W_MM_ENC : POOL32A_3RB0_FMT<"precrq.ph.w", 0b0011101101>;
class PRECRQ_QB_PH_MM_ENC : POOL32A_3RB0_FMT<"precrq.qb.ph", 0b0010101101>;
class PRECRQU_S_QB_PH_MM_ENC
: POOL32A_3RB0_FMT<"precrqu_s.qb.ph", 0b0101101101>;
class PRECRQ_RS_PH_W_MM_ENC : POOL32A_3RB0_FMT<"precrq_rs.ph.w", 0b0100101101>;
// Instruction desc.
class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
@ -354,6 +364,10 @@ def MULEQ_S_W_PHR_MM : DspMMRel, MULEQ_S_W_PHR_MM_ENC, MULEQ_S_W_PHR_DESC;
def MULEU_S_PH_QBL_MM : DspMMRel, MULEU_S_PH_QBL_MM_ENC, MULEU_S_PH_QBL_DESC;
def MULEU_S_PH_QBR_MM : DspMMRel, MULEU_S_PH_QBR_MM_ENC, MULEU_S_PH_QBR_DESC;
def MULQ_RS_PH_MM : DspMMRel, MULQ_RS_PH_MM_ENC, MULQ_RS_PH_DESC;
def PRECRQ_PH_W_MM : DspMMRel, PRECRQ_PH_W_MM_ENC, PRECRQ_PH_W_DESC;
def PRECRQ_QB_PH_MM : DspMMRel, PRECRQ_QB_PH_MM_ENC, PRECRQ_QB_PH_DESC;
def PRECRQU_S_QB_PH_MM : DspMMRel, PRECRQU_S_QB_PH_MM_ENC, PRECRQU_S_QB_PH_DESC;
def PRECRQ_RS_PH_W_MM : DspMMRel, PRECRQ_RS_PH_W_MM_ENC, PRECRQ_RS_PH_W_DESC;
// microMIPS DSP Rev 2
def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
ISA_DSPR2;
@ -398,3 +412,9 @@ def MUL_S_PH_MMR2 : DspMMRel, MUL_S_PH_MMR2_ENC, MUL_S_PH_DESC, ISA_DSPR2;
def MULQ_RS_W_MMR2 : DspMMRel, MULQ_RS_W_MMR2_ENC, MULQ_RS_W_DESC, ISA_DSPR2;
def MULQ_S_PH_MMR2 : DspMMRel, MULQ_S_PH_MMR2_ENC, MULQ_S_PH_DESC, ISA_DSPR2;
def MULQ_S_W_MMR2 : DspMMRel, MULQ_S_W_MMR2_ENC, MULQ_S_W_DESC, ISA_DSPR2;
def PRECR_QB_PH_MMR2 : DspMMRel, PRECR_QB_PH_MMR2_ENC, PRECR_QB_PH_DESC,
ISA_DSPR2;
def PRECR_SRA_PH_W_MMR2 : DspMMRel, PRECR_SRA_PH_W_MMR2_ENC,
PRECR_SRA_PH_W_DESC, ISA_DSPR2;
def PRECR_SRA_R_PH_W_MMR2 : DspMMRel, PRECR_SRA_R_PH_W_MMR2_ENC,
PRECR_SRA_R_PH_W_DESC, ISA_DSPR2;

16
lib/Target/Mips/MipsDSPInstrInfo.td
View File

@ -295,6 +295,7 @@ class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
}
class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
@ -306,6 +307,7 @@ class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
InstrItinClass Itinerary = itin;
string Constraints = "$src = $rt";
string BaseOpcode = instr_asm;
}
class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
@ -1105,10 +1107,10 @@ def MODSUB : MODSUB_ENC, MODSUB_DESC;
def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
def PRECRQ_QB_PH : DspMMRel, PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
def PRECRQ_PH_W : DspMMRel, PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
def PRECRQ_RS_PH_W : DspMMRel, PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
def PRECRQU_S_QB_PH : DspMMRel, PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
def PRECEQ_W_PHL : DspMMRel, PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
def PRECEQ_W_PHR : DspMMRel, PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
def PRECEQU_PH_QBL : DspMMRel, PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
@ -1240,9 +1242,9 @@ def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC;
def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
def PRECR_QB_PH : DspMMRel, PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
def PRECR_SRA_PH_W : DspMMRel, PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
def PRECR_SRA_R_PH_W : DspMMRel, PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC;
def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC;
def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC;

4
test/MC/Disassembler/Mips/micromips-dsp/valid.txt
View File

@ -42,6 +42,10 @@
0x01 0xf0 0xb3 0x3c # CHECK: preceu.ph.qbla $15, $16
0x02 0x32 0xd1 0x3c # CHECK: preceu.ph.qbr $17, $18
0x02 0x74 0xd3 0x3c # CHECK: preceu.ph.qbra $19, $20
0x01 0x49 0x40 0xed # CHECK: precrq.ph.w $8, $9, $10
0x01 0xac 0x58 0xad # CHECK: precrq.qb.ph $11, $12, $13
0x02 0x0f 0x71 0x6d # CHECK: precrqu_s.qb.ph $14, $15, $16
0x02 0x72 0x89 0x2d # CHECK: precrq_rs.ph.w $17, $18, $19
0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5
0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5
0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5

7
test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
View File

@ -55,6 +55,13 @@
0x01 0xf0 0xb3 0x3c # CHECK: preceu.ph.qbla $15, $16
0x02 0x32 0xd1 0x3c # CHECK: preceu.ph.qbr $17, $18
0x02 0x74 0xd3 0x3c # CHECK: preceu.ph.qbra $19, $20
0x00 0x62 0x08 0x6d # CHECK: precr.qb.ph $1, $2, $3
0x00 0x85 0x0b 0xcd # CHECK: precr_sra.ph.w $4, $5, 1
0x00 0xc7 0x17 0xcd # CHECK: precr_sra_r.ph.w $6, $7, 2
0x01 0x49 0x40 0xed # CHECK: precrq.ph.w $8, $9, $10
0x01 0xac 0x58 0xad # CHECK: precrq.qb.ph $11, $12, $13
0x02 0x0f 0x71 0x6d # CHECK: precrqu_s.qb.ph $14, $15, $16
0x02 0x72 0x89 0x2d # CHECK: precrq_rs.ph.w $17, $18, $19
0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5
0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5
0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5

4
test/MC/Mips/micromips-dsp/valid.s
View File

@ -43,6 +43,10 @@
preceu.ph.qbla $15, $16 # CHECK: preceu.ph.qbla $15, $16 # encoding: [0x01,0xf0,0xb3,0x3c]
preceu.ph.qbr $17, $18 # CHECK: preceu.ph.qbr $17, $18 # encoding: [0x02,0x32,0xd1,0x3c]
preceu.ph.qbra $19, $20 # CHECK: preceu.ph.qbra $19, $20 # encoding: [0x02,0x74,0xd3,0x3c]
precrq.ph.w $8, $9, $10 # CHECK: precrq.ph.w $8, $9, $10 # encoding: [0x01,0x49,0x40,0xed]
precrq.qb.ph $11, $12, $13 # CHECK: precrq.qb.ph $11, $12, $13 # encoding: [0x01,0xac,0x58,0xad]
precrqu_s.qb.ph $14, $15, $16 # CHECK: precrqu_s.qb.ph $14, $15, $16 # encoding: [0x02,0x0f,0x71,0x6d]
precrq_rs.ph.w $17, $18, $19 # CHECK: precrq_rs.ph.w $17, $18, $19 # encoding: [0x02,0x72,0x89,0x2d]
shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5]
shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5]
shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c]

7
test/MC/Mips/micromips-dspr2/valid.s
View File

@ -56,6 +56,13 @@
preceu.ph.qbla $15, $16 # CHECK: preceu.ph.qbla $15, $16 # encoding: [0x01,0xf0,0xb3,0x3c]
preceu.ph.qbr $17, $18 # CHECK: preceu.ph.qbr $17, $18 # encoding: [0x02,0x32,0xd1,0x3c]
preceu.ph.qbra $19, $20 # CHECK: preceu.ph.qbra $19, $20 # encoding: [0x02,0x74,0xd3,0x3c]
precr.qb.ph $1, $2, $3 # CHECK: precr.qb.ph $1, $2, $3 # encoding: [0x00,0x62,0x08,0x6d]
precr_sra.ph.w $4, $5, 1 # CHECK: precr_sra.ph.w $4, $5, 1 # encoding: [0x00,0x85,0x0b,0xcd]
precr_sra_r.ph.w $6, $7, 2 # CHECK: precr_sra_r.ph.w $6, $7, 2 # encoding: [0x00,0xc7,0x17,0xcd]
precrq.ph.w $8, $9, $10 # CHECK: precrq.ph.w $8, $9, $10 # encoding: [0x01,0x49,0x40,0xed]
precrq.qb.ph $11, $12, $13 # CHECK: precrq.qb.ph $11, $12, $13 # encoding: [0x01,0xac,0x58,0xad]
precrqu_s.qb.ph $14, $15, $16 # CHECK: precrqu_s.qb.ph $14, $15, $16 # encoding: [0x02,0x0f,0x71,0x6d]
precrq_rs.ph.w $17, $18, $19 # CHECK: precrq_rs.ph.w $17, $18, $19 # encoding: [0x02,0x72,0x89,0x2d]
shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5]
shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5]
shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c]