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[RFC][Patch 1/3] Add a new class of predicates for variant scheduling classes.
This patch is the first of a sequence of three patches described by the LLVM-dev RFC "MC support for variant scheduling classes". http://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html The goal of this patch is to introduce a new class of scheduling predicates for SchedReadVariant and SchedWriteVariant. An MCSchedPredicate can be used instead of a normal SchedPredicate to model checks on the instruction (either a MachineInstr or a MCInst). Internally, an MCSchedPredicate encapsulates an MCInstPredicate definition. MCInstPredicate allows the definition of expressions with a well-known semantic, that can be used to generate code for both MachineInstr and MCInst. This is the first step toward teaching to tools like lllvm-mca how to resolve variant scheduling classes. Differential Revision: https://reviews.llvm.org/D46695 llvm-svn: 333282
This commit is contained in:
Andrea Di Biagio
parent
e24fbae7ce
commit
c26fd3adc6
@ -383,6 +383,11 @@ class DwarfRegAlias<Register reg> {
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Register DwarfAlias = reg;
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}
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//===----------------------------------------------------------------------===//
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// Pull in the common support for MCPredicate (portable scheduling predicates).
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//
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include "llvm/Target/TargetInstrPredicate.td"
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//===----------------------------------------------------------------------===//
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// Pull in the common support for scheduling
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//
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194
include/llvm/Target/TargetInstrPredicate.td
Normal file
194
include/llvm/Target/TargetInstrPredicate.td
Normal file
@ -0,0 +1,194 @@
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//===- TargetInstrPredicate.td - ---------------------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines MCInstPredicate classes and its subclasses.
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//
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// MCInstPredicate is used to describe constraints on the opcode/operand(s) of
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// an instruction. Each MCInstPredicate class has a well-known semantic, and it
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// is used by a PredicateExpander to generate code for MachineInstr and/or
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// MCInst.
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//
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// MCInstPredicate definitions can be used to construct MCSchedPredicate
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// definitions. An MCSchedPredicate can be used in place of a SchedPredicate
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// when defining SchedReadVariant and SchedWriteVariant used by a processor
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// scheduling model.
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//
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// Here is an example of MCInstPredicate definition:
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//
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// def MCInstPredicateExample : CheckAll<[
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// CheckOpcode<[BLR]>,
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// CheckIsRegOperand<0>,
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// CheckNot<CheckRegOperand<0, LR>>]>;
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//
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// Predicate `MCInstPredicateExample` checks that the machine instruction in
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// input is a BLR, and that operand at index 0 is register `LR`.
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//
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// That predicate could be used to rewrite the following definition (from
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// AArch64SchedExynosM3.td):
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//
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// def M3BranchLinkFastPred : SchedPredicate<[{
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// MI->getOpcode() == AArch64::BLR &&
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// MI->getOperand(0).isReg() &&
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// MI->getOperand(0).getReg() != AArch64::LR}]>;
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//
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// MCInstPredicate definitions are used to construct MCSchedPredicate (see the
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// definition of class MCSchedPredicate in llvm/Target/TargetSchedule.td). An
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// MCSchedPredicate can be used by a `SchedVar` to associate a predicate with a
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// list of SchedReadWrites. Note that `SchedVar` are used to create SchedVariant
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// definitions.
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//
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// Each MCInstPredicate class has a well known semantic. For example,
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// `CheckOpcode` is only used to check the instruction opcode value.
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//
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// MCInstPredicate classes allow the definition of predicates in a declarative
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// way. These predicates don't require a custom block of C++, and can be used
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// to define conditions on instructions without being bound to a particular
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// representation (i.e. MachineInstr vs MCInst).
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//
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// It also means that tablegen backends must know how to parse and expand them
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// into code that works on MCInst (or MachineInst).
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//
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// Instances of class PredicateExpander (see utils/Tablegen/PredicateExpander.h)
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// know how to expand a predicate. For each MCInstPredicate class, there must be
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// an "expand" method available in the PredicateExpander interface.
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//
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// For example, a `CheckOpcode` predicate is expanded using method
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// `PredicateExpander::expandCheckOpcode()`.
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//
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// New MCInstPredicate classes must be added to this file. For each new class
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// XYZ, an "expandXYZ" method must be added to the PredicateExpander.
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//
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//===----------------------------------------------------------------------===//
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// Forward declarations.
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class Instruction;
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// A generic machine instruction predicate.
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class MCInstPredicate;
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class MCTrue : MCInstPredicate; // A predicate that always evaluates to True.
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class MCFalse : MCInstPredicate; // A predicate that always evaluates to False.
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def TruePred : MCTrue;
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def FalsePred : MCFalse;
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// A predicate used to negate the outcome of another predicate.
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// It allows to easily express "set difference" operations. For example, it
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// makes it easy to describe a check that tests if an opcode is not part of a
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// set of opcodes.
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class CheckNot<MCInstPredicate P> : MCInstPredicate {
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MCInstPredicate Pred = P;
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}
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// This class is used as a building block to define predicates on instruction
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// operands. It is used to reference a specific machine operand.
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class MCOperandPredicate<int Index> : MCInstPredicate {
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int OpIndex = Index;
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}
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// Return true if machine operand at position `Index` is a register operand.
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class CheckIsRegOperand<int Index> : MCOperandPredicate<Index>;
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// Return true if machine operand at position `Index` is an immediate operand.
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class CheckIsImmOperand<int Index> : MCOperandPredicate<Index>;
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// Check if machine operands at index `First` and index `Second` both reference
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// the same register.
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class CheckSameRegOperand<int First, int Second> : MCInstPredicate {
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int FirstIndex = First;
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int SecondIndex = Second;
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}
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// Check that the machine register operand at position `Index` references
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// register R. This predicate assumes that we already checked that the machine
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// operand at position `Index` is a register operand.
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class CheckRegOperand<int Index, Register R> : MCOperandPredicate<Index> {
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Register Reg = R;
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}
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// Check that the operand at position `Index` is immediate `Imm`.
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class CheckImmOperand<int Index, int Imm> : MCOperandPredicate<Index> {
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int ImmVal = Imm;
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}
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// Similar to CheckImmOperand, however the immediate is not a literal number.
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// This is useful when we want to compare the value of an operand against an
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// enum value, and we know the actual integer value of that enum.
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class CheckImmOperand_s<int Index, string Value> : MCOperandPredicate<Index> {
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string ImmVal = Value;
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}
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// Check that the operand at position `Index` is immediate value zero.
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class CheckZeroOperand<int Index> : CheckImmOperand<Index, 0>;
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// Check that the instruction has exactly `Num` operands.
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class CheckNumOperands<int Num> : MCInstPredicate {
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int NumOps = Num;
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}
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// Check that the instruction opcode is one of the opcodes in set `Opcodes`.
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// This is a simple set membership query. The easier way to check if an opcode
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// is not a member of the set is by using a `CheckNot<CheckOpcode<[...]>>`
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// sequence.
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class CheckOpcode<list<Instruction> Opcodes> : MCInstPredicate {
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list<Instruction> ValidOpcodes = Opcodes;
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}
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// Check that the instruction opcode is a pseudo opcode member of the set
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// `Opcodes`. This check is always expanded to "false" if we are generating
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// code for MCInst.
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class CheckPseudo<list<Instruction> Opcodes> : CheckOpcode<Opcodes>;
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// A non-portable predicate. Only to use as a last resort when a block of code
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// cannot possibly be converted in a declarative way using other MCInstPredicate
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// classes. This check is always expanded to "false" when generating code for
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// MCInst.
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class CheckNonPortable<string Code> : MCInstPredicate {
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string CodeBlock = Code;
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}
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// A sequence of predicates. It is used as the base class for CheckAll, and
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// CheckAny. It allows to describe compositions of predicates.
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class CheckPredicateSequence<list<MCInstPredicate> Preds> : MCInstPredicate {
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list<MCInstPredicate> Predicates = Preds;
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}
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// Check that all of the predicates in `Preds` evaluate to true.
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class CheckAll<list<MCInstPredicate> Sequence>
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: CheckPredicateSequence<Sequence>;
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// Check that at least one of the predicates in `Preds` evaluates to true.
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class CheckAny<list<MCInstPredicate> Sequence>
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: CheckPredicateSequence<Sequence>;
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// Check that a call to method `Name` in class "XXXGenInstrInfo" (where XXX is
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// the `Target` name) returns true.
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//
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// TIIPredicate definitions are used to model calls to the target-specific
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// InstrInfo. A TIIPredicate is treated specially by the InstrInfoEmitter
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// tablegen backend, which will use it to automatically generate a definition in
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// the target specific `GenInstrInfo` class.
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class TIIPredicate<string Target, string Name, MCInstPredicate P> : MCInstPredicate {
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string TargetName = Target;
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string FunctionName = Name;
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MCInstPredicate Pred = P;
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}
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// A function predicate that takes as input a machine instruction, and returns
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// a boolean value.
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//
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// This predicate is expanded into a function call by the PredicateExpander.
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// In particular, the PredicateExpander would either expand this predicate into
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// a call to `MCInstFn`, or into a call to`MachineInstrFn` depending on whether
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// it is lowering predicates for MCInst or MachineInstr.
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//
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// In this context, `MCInstFn` and `MachineInstrFn` are both function names.
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class CheckFunctionPredicate<string MCInstFn, string MachineInstrFn> : MCInstPredicate {
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string MCInstFnName = MCInstFn;
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string MachineInstrFnName = MachineInstrFn;
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}
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@ -355,13 +355,23 @@ class PredicateProlog<code c> {
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code Code = c;
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}
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// Base class for scheduling predicates.
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class SchedPredicateBase;
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// A scheduling predicate whose logic is defined by a MCInstPredicate.
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// This can directly be used by SchedWriteVariant definitions.
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class MCSchedPredicate<MCInstPredicate P> : SchedPredicateBase {
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MCInstPredicate Pred = P;
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SchedMachineModel SchedModel = ?;
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}
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// Define a predicate to determine which SchedVariant applies to a
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// particular MachineInstr. The code snippet is used as an
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// if-statement's expression. Available variables are MI, SchedModel,
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// and anything defined in a PredicateProlog.
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//
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// SchedModel silences warnings but is ignored.
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class SchedPredicate<code pred> {
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class SchedPredicate<code pred> : SchedPredicateBase {
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SchedMachineModel SchedModel = ?;
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code Predicate = pred;
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}
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@ -376,8 +386,8 @@ def NoSchedPred : SchedPredicate<[{true}]>;
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// operands. In this case, latency is not additive. If the current Variant
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// is already part of a Sequence, then that entire chain leading up to
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// the Variant is distributed over the variadic operands.
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class SchedVar<SchedPredicate pred, list<SchedReadWrite> selected> {
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SchedPredicate Predicate = pred;
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class SchedVar<SchedPredicateBase pred, list<SchedReadWrite> selected> {
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SchedPredicateBase Predicate = pred;
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list<SchedReadWrite> Selected = selected;
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}
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@ -29,6 +29,7 @@ add_tablegen(llvm-tblgen LLVM
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InstrDocsEmitter.cpp
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IntrinsicEmitter.cpp
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OptParserEmitter.cpp
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PredicateExpander.cpp
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PseudoLoweringEmitter.cpp
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RISCVCompressInstEmitter.cpp
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RegisterBankEmitter.cpp
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@ -16,6 +16,7 @@
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#include "CodeGenInstruction.h"
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#include "CodeGenSchedule.h"
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#include "CodeGenTarget.h"
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#include "PredicateExpander.h"
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#include "SequenceToOffsetTable.h"
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#include "TableGenBackends.h"
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#include "llvm/ADT/ArrayRef.h"
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@ -59,6 +60,13 @@ private:
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typedef std::map<std::map<unsigned, unsigned>,
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std::vector<std::string>> OpNameMapTy;
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typedef std::map<std::string, unsigned>::iterator StrUintMapIter;
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/// Generate member functions in the target-specific GenInstrInfo class.
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///
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/// This method is used to custom expand TIIPredicate definitions.
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/// See file llvm/Target/TargetInstPredicates.td for a description of what is
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/// a TIIPredicate and how to use it.
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void emitTIIHelperMethods(raw_ostream &OS);
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void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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Record *InstrInfo,
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std::map<std::vector<Record*>, unsigned> &EL,
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@ -339,6 +347,25 @@ void InstrInfoEmitter::emitOperandTypesEnum(raw_ostream &OS,
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OS << "#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM\n\n";
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}
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void InstrInfoEmitter::emitTIIHelperMethods(raw_ostream &OS) {
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RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
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if (TIIPredicates.empty())
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return;
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formatted_raw_ostream FOS(OS);
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PredicateExpander PE;
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PE.setExpandForMC(false);
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PE.setIndentLevel(2);
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for (const Record *Rec : TIIPredicates) {
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FOS << "\n static bool " << Rec->getValueAsString("FunctionName");
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FOS << "(const MachineInstr &MI) {\n";
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FOS << " return ";
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PE.expandPredicate(FOS, Rec->getValueAsDef("Pred"));
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FOS << ";\n }\n";
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}
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}
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//===----------------------------------------------------------------------===//
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// Main Output.
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//===----------------------------------------------------------------------===//
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@ -435,9 +462,11 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
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OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
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<< " explicit " << ClassName
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<< "(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);\n"
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<< " ~" << ClassName << "() override = default;\n"
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<< "};\n";
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OS << "} // end llvm namespace\n";
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<< " ~" << ClassName << "() override = default;\n";
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emitTIIHelperMethods(OS);
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OS << "\n};\n} // end llvm namespace\n";
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OS << "#endif // GET_INSTRINFO_HEADER\n\n";
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253
utils/TableGen/PredicateExpander.cpp
Normal file
253
utils/TableGen/PredicateExpander.cpp
Normal file
@ -0,0 +1,253 @@
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//===--------------------- PredicateExpander.cpp --------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// Functionalities used by the Tablegen backends to expand machine predicates.
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//
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//===----------------------------------------------------------------------===//
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#include "PredicateExpander.h"
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namespace llvm {
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void PredicateExpander::expandTrue(formatted_raw_ostream &OS) { OS << "true"; }
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void PredicateExpander::expandFalse(formatted_raw_ostream &OS) {
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OS << "false";
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}
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void PredicateExpander::expandCheckImmOperand(formatted_raw_ostream &OS,
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int OpIndex, int ImmVal) {
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OS << "MI.getOperand(" << OpIndex << ").getImm() "
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<< (shouldNegate() ? "!= " : "== ") << ImmVal;
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}
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void PredicateExpander::expandCheckImmOperand(formatted_raw_ostream &OS,
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int OpIndex, StringRef ImmVal) {
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OS << "MI.getOperand(" << OpIndex << ").getImm() "
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<< (shouldNegate() ? "!= " : "== ") << ImmVal;
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}
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void PredicateExpander::expandCheckRegOperand(formatted_raw_ostream &OS,
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int OpIndex, const Record *Reg) {
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assert(Reg->isSubClassOf("Register") && "Expected a register Record!");
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OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex
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<< ").getReg() " << (shouldNegate() ? "!= " : "== ");
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const StringRef Str = Reg->getValueAsString("Namespace");
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if (!Str.empty())
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OS << Str << "::";
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OS << Reg->getName();
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}
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void PredicateExpander::expandCheckSameRegOperand(formatted_raw_ostream &OS,
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int First, int Second) {
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OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << First
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<< ").getReg() " << (shouldNegate() ? "!=" : "==") << " MI"
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<< (isByRef() ? "." : "->") << "getOperand(" << Second << ").getReg()";
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}
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void PredicateExpander::expandCheckNumOperands(formatted_raw_ostream &OS,
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int NumOps) {
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OS << "MI" << (isByRef() ? "." : "->") << "getNumOperands() "
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<< (shouldNegate() ? "!= " : "== ") << NumOps;
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}
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void PredicateExpander::expandCheckOpcode(formatted_raw_ostream &OS,
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const Record *Inst) {
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OS << "MI" << (isByRef() ? "." : "->") << "getOpcode() "
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<< (shouldNegate() ? "!= " : "== ") << Inst->getValueAsString("Namespace")
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<< "::" << Inst->getName();
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}
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void PredicateExpander::expandCheckOpcode(formatted_raw_ostream &OS,
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const RecVec &Opcodes) {
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assert(!Opcodes.empty() && "Expected at least one opcode to check!");
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bool First = true;
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if (Opcodes.size() == 1) {
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OS << "( ";
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expandCheckOpcode(OS, Opcodes[0]);
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OS << " )";
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return;
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}
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OS << '(';
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increaseIndentLevel();
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for (const Record *Rec : Opcodes) {
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OS << '\n';
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OS.PadToColumn(getIndentLevel() * 2);
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if (!First)
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OS << (shouldNegate() ? "&& " : "|| ");
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expandCheckOpcode(OS, Rec);
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First = false;
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}
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OS << '\n';
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decreaseIndentLevel();
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OS.PadToColumn(getIndentLevel() * 2);
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OS << ')';
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}
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void PredicateExpander::expandCheckPseudo(formatted_raw_ostream &OS,
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const RecVec &Opcodes) {
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if (shouldExpandForMC())
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expandFalse(OS);
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else
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expandCheckOpcode(OS, Opcodes);
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}
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void PredicateExpander::expandPredicateSequence(formatted_raw_ostream &OS,
|
||||
const RecVec &Sequence,
|
||||
bool IsCheckAll) {
|
||||
assert(!Sequence.empty() && "Found an invalid empty predicate set!");
|
||||
if (Sequence.size() == 1)
|
||||
return expandPredicate(OS, Sequence[0]);
|
||||
|
||||
// Okay, there is more than one predicate in the set.
|
||||
bool First = true;
|
||||
OS << (shouldNegate() ? "!(" : "(");
|
||||
increaseIndentLevel();
|
||||
|
||||
bool OldValue = shouldNegate();
|
||||
setNegatePredicate(false);
|
||||
for (const Record *Rec : Sequence) {
|
||||
OS << '\n';
|
||||
OS.PadToColumn(getIndentLevel() * 2);
|
||||
if (!First)
|
||||
OS << (IsCheckAll ? "&& " : "|| ");
|
||||
expandPredicate(OS, Rec);
|
||||
First = false;
|
||||
}
|
||||
OS << '\n';
|
||||
decreaseIndentLevel();
|
||||
OS.PadToColumn(getIndentLevel() * 2);
|
||||
OS << ')';
|
||||
setNegatePredicate(OldValue);
|
||||
}
|
||||
|
||||
void PredicateExpander::expandTIIFunctionCall(formatted_raw_ostream &OS,
|
||||
StringRef TargetName,
|
||||
StringRef MethodName) {
|
||||
OS << (shouldNegate() ? "!" : "");
|
||||
if (shouldExpandForMC())
|
||||
OS << TargetName << "_MC::";
|
||||
else
|
||||
OS << TargetName << "Gen"
|
||||
<< "InstrInfo::";
|
||||
OS << MethodName << (isByRef() ? "(MI)" : "(*MI)");
|
||||
}
|
||||
|
||||
void PredicateExpander::expandCheckIsRegOperand(formatted_raw_ostream &OS,
|
||||
int OpIndex) {
|
||||
OS << (shouldNegate() ? "!" : "") << "MI" << (isByRef() ? "." : "->")
|
||||
<< "getOperand(" << OpIndex << ").isReg() ";
|
||||
}
|
||||
|
||||
void PredicateExpander::expandCheckIsImmOperand(formatted_raw_ostream &OS,
|
||||
int OpIndex) {
|
||||
OS << (shouldNegate() ? "!" : "") << "MI" << (isByRef() ? "." : "->")
|
||||
<< "getOperand(" << OpIndex << ").isImm() ";
|
||||
}
|
||||
|
||||
void PredicateExpander::expandCheckFunctionPredicate(formatted_raw_ostream &OS,
|
||||
StringRef MCInstFn,
|
||||
StringRef MachineInstrFn) {
|
||||
OS << (shouldExpandForMC() ? MCInstFn : MachineInstrFn)
|
||||
<< (isByRef() ? "(MI)" : "(*MI)");
|
||||
}
|
||||
|
||||
void PredicateExpander::expandCheckNonPortable(formatted_raw_ostream &OS,
|
||||
StringRef Code) {
|
||||
if (shouldExpandForMC())
|
||||
return expandFalse(OS);
|
||||
|
||||
OS << '(' << Code << ')';
|
||||
}
|
||||
|
||||
void PredicateExpander::expandPredicate(formatted_raw_ostream &OS,
|
||||
const Record *Rec) {
|
||||
OS.flush();
|
||||
unsigned ColNum = getIndentLevel() * 2;
|
||||
if (OS.getColumn() < ColNum)
|
||||
OS.PadToColumn(ColNum);
|
||||
|
||||
if (Rec->isSubClassOf("MCTrue")) {
|
||||
if (shouldNegate())
|
||||
return expandFalse(OS);
|
||||
return expandTrue(OS);
|
||||
}
|
||||
|
||||
if (Rec->isSubClassOf("MCFalse")) {
|
||||
if (shouldNegate())
|
||||
return expandTrue(OS);
|
||||
return expandFalse(OS);
|
||||
}
|
||||
|
||||
if (Rec->isSubClassOf("CheckNot")) {
|
||||
flipNegatePredicate();
|
||||
expandPredicate(OS, Rec->getValueAsDef("Pred"));
|
||||
flipNegatePredicate();
|
||||
return;
|
||||
}
|
||||
|
||||
if (Rec->isSubClassOf("CheckIsRegOperand"))
|
||||
return expandCheckIsRegOperand(OS, Rec->getValueAsInt("OpIndex"));
|
||||
|
||||
if (Rec->isSubClassOf("CheckIsImmOperand"))
|
||||
return expandCheckIsImmOperand(OS, Rec->getValueAsInt("OpIndex"));
|
||||
|
||||
if (Rec->isSubClassOf("CheckRegOperand"))
|
||||
return expandCheckRegOperand(OS, Rec->getValueAsInt("OpIndex"),
|
||||
Rec->getValueAsDef("Reg"));
|
||||
|
||||
if (Rec->isSubClassOf("CheckImmOperand"))
|
||||
return expandCheckImmOperand(OS, Rec->getValueAsInt("OpIndex"),
|
||||
Rec->getValueAsInt("ImmVal"));
|
||||
|
||||
if (Rec->isSubClassOf("CheckImmOperand_s"))
|
||||
return expandCheckImmOperand(OS, Rec->getValueAsInt("OpIndex"),
|
||||
Rec->getValueAsString("ImmVal"));
|
||||
|
||||
if (Rec->isSubClassOf("CheckSameRegOperand"))
|
||||
return expandCheckSameRegOperand(OS, Rec->getValueAsInt("FirstIndex"),
|
||||
Rec->getValueAsInt("SecondIndex"));
|
||||
|
||||
if (Rec->isSubClassOf("CheckNumOperands"))
|
||||
return expandCheckNumOperands(OS, Rec->getValueAsInt("NumOps"));
|
||||
|
||||
if (Rec->isSubClassOf("CheckPseudo"))
|
||||
return expandCheckPseudo(OS, Rec->getValueAsListOfDefs("ValidOpcodes"));
|
||||
|
||||
if (Rec->isSubClassOf("CheckOpcode"))
|
||||
return expandCheckOpcode(OS, Rec->getValueAsListOfDefs("ValidOpcodes"));
|
||||
|
||||
if (Rec->isSubClassOf("CheckAll"))
|
||||
return expandPredicateSequence(OS, Rec->getValueAsListOfDefs("Predicates"),
|
||||
/* AllOf */ true);
|
||||
|
||||
if (Rec->isSubClassOf("CheckAny"))
|
||||
return expandPredicateSequence(OS, Rec->getValueAsListOfDefs("Predicates"),
|
||||
/* AllOf */ false);
|
||||
|
||||
if (Rec->isSubClassOf("CheckFunctionPredicate"))
|
||||
return expandCheckFunctionPredicate(
|
||||
OS, Rec->getValueAsString("MCInstFnName"),
|
||||
Rec->getValueAsString("MachineInstrFnName"));
|
||||
|
||||
if (Rec->isSubClassOf("CheckNonPortable"))
|
||||
return expandCheckNonPortable(OS, Rec->getValueAsString("CodeBlock"));
|
||||
|
||||
if (Rec->isSubClassOf("TIIPredicate"))
|
||||
return expandTIIFunctionCall(OS, Rec->getValueAsString("TargetName"),
|
||||
Rec->getValueAsString("FunctionName"));
|
||||
|
||||
llvm_unreachable("No known rules to expand this MCInstPredicate");
|
||||
}
|
||||
|
||||
} // namespace llvm
|
||||
85
utils/TableGen/PredicateExpander.h
Normal file
85
utils/TableGen/PredicateExpander.h
Normal file
@ -0,0 +1,85 @@
|
||||
//===--------------------- PredicateExpander.h ----------------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
/// \file
|
||||
/// Functionalities used by the Tablegen backends to expand machine predicates.
|
||||
///
|
||||
/// See file llvm/Target/TargetInstrPredicate.td for a full list and description
|
||||
/// of all the supported MCInstPredicate classes.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef LLVM_UTILS_TABLEGEN_PREDICATEEXPANDER_H
|
||||
#define LLVM_UTILS_TABLEGEN_PREDICATEEXPANDER_H
|
||||
|
||||
#include "llvm/ADT/StringRef.h"
|
||||
#include "llvm/Support/FormattedStream.h"
|
||||
#include "llvm/TableGen/Record.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class formatted_raw_ostream;
|
||||
|
||||
class PredicateExpander {
|
||||
bool EmitCallsByRef;
|
||||
bool NegatePredicate;
|
||||
bool ExpandForMC;
|
||||
unsigned IndentLevel;
|
||||
|
||||
PredicateExpander(const PredicateExpander &) = delete;
|
||||
PredicateExpander &operator=(const PredicateExpander &) = delete;
|
||||
|
||||
public:
|
||||
PredicateExpander()
|
||||
: EmitCallsByRef(true), NegatePredicate(false), ExpandForMC(false),
|
||||
IndentLevel(1U) {}
|
||||
bool isByRef() const { return EmitCallsByRef; }
|
||||
bool shouldNegate() const { return NegatePredicate; }
|
||||
bool shouldExpandForMC() const { return ExpandForMC; }
|
||||
unsigned getIndentLevel() const { return IndentLevel; }
|
||||
|
||||
void setByRef(bool Value) { EmitCallsByRef = Value; }
|
||||
void flipNegatePredicate() { NegatePredicate = !NegatePredicate; }
|
||||
void setNegatePredicate(bool Value) { NegatePredicate = Value; }
|
||||
void setExpandForMC(bool Value) { ExpandForMC = Value; }
|
||||
void increaseIndentLevel() { ++IndentLevel; }
|
||||
void decreaseIndentLevel() { --IndentLevel; }
|
||||
void setIndentLevel(unsigned Level) { IndentLevel = Level; }
|
||||
|
||||
using RecVec = std::vector<Record *>;
|
||||
void expandTrue(formatted_raw_ostream &OS);
|
||||
void expandFalse(formatted_raw_ostream &OS);
|
||||
void expandCheckImmOperand(formatted_raw_ostream &OS, int OpIndex,
|
||||
int ImmVal);
|
||||
void expandCheckImmOperand(formatted_raw_ostream &OS, int OpIndex,
|
||||
StringRef ImmVal);
|
||||
void expandCheckRegOperand(formatted_raw_ostream &OS, int OpIndex,
|
||||
const Record *Reg);
|
||||
void expandCheckSameRegOperand(formatted_raw_ostream &OS, int First,
|
||||
int Second);
|
||||
void expandCheckNumOperands(formatted_raw_ostream &OS, int NumOps);
|
||||
void expandCheckOpcode(formatted_raw_ostream &OS, const Record *Inst);
|
||||
|
||||
void expandCheckPseudo(formatted_raw_ostream &OS, const RecVec &Opcodes);
|
||||
void expandCheckOpcode(formatted_raw_ostream &OS, const RecVec &Opcodes);
|
||||
void expandPredicateSequence(formatted_raw_ostream &OS,
|
||||
const RecVec &Sequence, bool IsCheckAll);
|
||||
void expandTIIFunctionCall(formatted_raw_ostream &OS, StringRef TargetName,
|
||||
StringRef MethodName);
|
||||
void expandCheckIsRegOperand(formatted_raw_ostream &OS, int OpIndex);
|
||||
void expandCheckIsImmOperand(formatted_raw_ostream &OS, int OpIndex);
|
||||
void expandCheckFunctionPredicate(formatted_raw_ostream &OS,
|
||||
StringRef MCInstFn,
|
||||
StringRef MachineInstrFn);
|
||||
void expandCheckNonPortable(formatted_raw_ostream &OS, StringRef CodeBlock);
|
||||
void expandPredicate(formatted_raw_ostream &OS, const Record *Rec);
|
||||
};
|
||||
|
||||
} // namespace llvm
|
||||
|
||||
#endif
|
||||
@ -13,6 +13,7 @@
|
||||
|
||||
#include "CodeGenTarget.h"
|
||||
#include "CodeGenSchedule.h"
|
||||
#include "PredicateExpander.h"
|
||||
#include "llvm/ADT/SmallPtrSet.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include "llvm/ADT/StringExtras.h"
|
||||
@ -112,6 +113,9 @@ class SubtargetEmitter {
|
||||
void EmitProcessorModels(raw_ostream &OS);
|
||||
void EmitProcessorLookup(raw_ostream &OS);
|
||||
void EmitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS);
|
||||
void emitSchedModelHelpersImpl(raw_ostream &OS,
|
||||
bool OnlyExpandMCInstPredicates = false);
|
||||
|
||||
void EmitSchedModel(raw_ostream &OS);
|
||||
void EmitHwModeCheck(const std::string &ClassName, raw_ostream &OS);
|
||||
void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures,
|
||||
@ -1461,35 +1465,37 @@ static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) {
|
||||
}
|
||||
|
||||
static void emitPredicates(const CodeGenSchedTransition &T,
|
||||
const CodeGenSchedClass &SC, unsigned ProcIdx,
|
||||
const CodeGenSchedClass &SC,
|
||||
PredicateExpander &PE,
|
||||
raw_ostream &OS) {
|
||||
if (ProcIdx && !count(T.ProcIndices, ProcIdx))
|
||||
return;
|
||||
|
||||
std::string Buffer;
|
||||
raw_string_ostream Stream(Buffer);
|
||||
Stream << " if (";
|
||||
raw_string_ostream StringStream(Buffer);
|
||||
formatted_raw_ostream FOS(StringStream);
|
||||
|
||||
FOS.PadToColumn(6);
|
||||
FOS << "if (";
|
||||
for (RecIter RI = T.PredTerm.begin(), RE = T.PredTerm.end(); RI != RE; ++RI) {
|
||||
if (RI != T.PredTerm.begin())
|
||||
Stream << "\n && ";
|
||||
Stream << "(" << (*RI)->getValueAsString("Predicate") << ")";
|
||||
if (RI != T.PredTerm.begin()) {
|
||||
FOS << "\n";
|
||||
FOS.PadToColumn(8);
|
||||
FOS << "&& ";
|
||||
}
|
||||
const Record *Rec = *RI;
|
||||
if (Rec->isSubClassOf("MCSchedPredicate"))
|
||||
PE.expandPredicate(FOS, Rec->getValueAsDef("Pred"));
|
||||
else
|
||||
FOS << "(" << Rec->getValueAsString("Predicate") << ")";
|
||||
}
|
||||
|
||||
Stream << ")\n"
|
||||
<< " return " << T.ToClassIdx << "; // " << SC.Name << '\n';
|
||||
Stream.flush();
|
||||
FOS << ")\n";
|
||||
FOS.PadToColumn(8);
|
||||
FOS << "return " << T.ToClassIdx << "; // " << SC.Name << '\n';
|
||||
FOS.flush();
|
||||
OS << Buffer;
|
||||
}
|
||||
|
||||
void SubtargetEmitter::EmitSchedModelHelpers(const std::string &ClassName,
|
||||
raw_ostream &OS) {
|
||||
OS << "unsigned " << ClassName
|
||||
<< "\n::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI,"
|
||||
<< " const TargetSchedModel *SchedModel) const {\n";
|
||||
|
||||
// Emit the predicate prolog code.
|
||||
emitPredicateProlog(Records, OS);
|
||||
|
||||
void SubtargetEmitter::emitSchedModelHelpersImpl(
|
||||
raw_ostream &OS, bool OnlyExpandMCInstPredicates) {
|
||||
// Collect Variant Classes.
|
||||
IdxVec VariantClasses;
|
||||
for (const CodeGenSchedClass &SC : SchedModels.schedClasses()) {
|
||||
@ -1503,24 +1509,43 @@ void SubtargetEmitter::EmitSchedModelHelpers(const std::string &ClassName,
|
||||
for (unsigned VC : VariantClasses) {
|
||||
// Emit code for each variant scheduling class.
|
||||
const CodeGenSchedClass &SC = SchedModels.getSchedClass(VC);
|
||||
OS << " case " << VC << ": // " << SC.Name << '\n';
|
||||
IdxVec ProcIndices;
|
||||
for (const CodeGenSchedTransition &T : SC.Transitions) {
|
||||
if (OnlyExpandMCInstPredicates &&
|
||||
!all_of(T.PredTerm, [](const Record *Rec) {
|
||||
return Rec->isSubClassOf("MCSchedPredicate");
|
||||
}))
|
||||
continue;
|
||||
|
||||
IdxVec PI;
|
||||
std::set_union(T.ProcIndices.begin(), T.ProcIndices.end(),
|
||||
ProcIndices.begin(), ProcIndices.end(),
|
||||
std::back_inserter(PI));
|
||||
ProcIndices.swap(PI);
|
||||
}
|
||||
if (ProcIndices.empty())
|
||||
continue;
|
||||
|
||||
OS << " case " << VC << ": // " << SC.Name << '\n';
|
||||
PredicateExpander PE;
|
||||
PE.setByRef(false);
|
||||
PE.setExpandForMC(OnlyExpandMCInstPredicates);
|
||||
for (unsigned PI : ProcIndices) {
|
||||
OS << " ";
|
||||
if (PI != 0)
|
||||
OS << "if (SchedModel->getProcessorID() == " << PI << ") ";
|
||||
OS << "{ // " << (SchedModels.procModelBegin() + PI)->ModelName
|
||||
<< '\n';
|
||||
if (PI != 0) {
|
||||
OS << (OnlyExpandMCInstPredicates
|
||||
? "if (CPUID == "
|
||||
: "if (SchedModel->getProcessorID() == ");
|
||||
OS << PI << ") ";
|
||||
}
|
||||
OS << "{ // " << (SchedModels.procModelBegin() + PI)->ModelName << '\n';
|
||||
|
||||
for (const CodeGenSchedTransition &T : SC.Transitions)
|
||||
emitPredicates(T, SchedModels.getSchedClass(T.ToClassIdx), PI, OS);
|
||||
for (const CodeGenSchedTransition &T : SC.Transitions) {
|
||||
if (PI != 0 && !count(T.ProcIndices, PI))
|
||||
continue;
|
||||
PE.setIndentLevel(4);
|
||||
emitPredicates(T, SchedModels.getSchedClass(T.ToClassIdx), PE, OS);
|
||||
}
|
||||
|
||||
OS << " }\n";
|
||||
if (PI == 0)
|
||||
@ -1532,8 +1557,29 @@ void SubtargetEmitter::EmitSchedModelHelpers(const std::string &ClassName,
|
||||
}
|
||||
OS << " };\n";
|
||||
}
|
||||
OS << " report_fatal_error(\"Expected a variant SchedClass\");\n"
|
||||
<< "} // " << ClassName << "::resolveSchedClass\n";
|
||||
|
||||
if (OnlyExpandMCInstPredicates) {
|
||||
OS << " // Don't know how to resolve this scheduling class.\n"
|
||||
<< " return 0;\n";
|
||||
return;
|
||||
}
|
||||
|
||||
OS << " report_fatal_error(\"Expected a variant SchedClass\");\n";
|
||||
}
|
||||
|
||||
void SubtargetEmitter::EmitSchedModelHelpers(const std::string &ClassName,
|
||||
raw_ostream &OS) {
|
||||
OS << "unsigned " << ClassName
|
||||
<< "\n::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI,"
|
||||
<< " const TargetSchedModel *SchedModel) const {\n";
|
||||
|
||||
// Emit the predicate prolog code.
|
||||
emitPredicateProlog(Records, OS);
|
||||
|
||||
// Emit target predicates.
|
||||
emitSchedModelHelpersImpl(OS);
|
||||
|
||||
OS << "} // " << ClassName << "::resolveSchedClass\n";
|
||||
}
|
||||
|
||||
void SubtargetEmitter::EmitHwModeCheck(const std::string &ClassName,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user