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TableGen: Privatize CodeGenRegisterClass::TheDef and Name.
When TableGen starts creating its own register classes, the synthesized classes won't have a Record reference. All register classes must have a name, though. llvm-svn: 141081
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1e0d8b4237
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c36b745e2e
@ -999,6 +999,10 @@ BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
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for (ArrayRef<CodeGenRegisterClass*>::const_iterator
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for (ArrayRef<CodeGenRegisterClass*>::const_iterator
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it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
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it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
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const CodeGenRegisterClass &RC = **it;
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const CodeGenRegisterClass &RC = **it;
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// Def will be NULL for non-user defined register classes.
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Record *Def = RC.getDef();
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if (!Def)
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continue;
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ClassInfo *CI = RegisterSetClasses[std::set<Record*>(RC.getOrder().begin(),
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ClassInfo *CI = RegisterSetClasses[std::set<Record*>(RC.getOrder().begin(),
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RC.getOrder().end())];
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RC.getOrder().end())];
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if (CI->ValueName.empty()) {
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if (CI->ValueName.empty()) {
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@ -1008,7 +1012,7 @@ BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
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} else
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} else
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CI->ValueName = CI->ValueName + "," + RC.getName();
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CI->ValueName = CI->ValueName + "," + RC.getName();
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RegisterClassClasses.insert(std::make_pair(RC.TheDef, CI));
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RegisterClassClasses.insert(std::make_pair(Def, CI));
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}
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}
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// Populate the map for individual registers.
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// Populate the map for individual registers.
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@ -712,7 +712,7 @@ void AsmWriterEmitter::EmitRegIsInRegClass(raw_ostream &O) {
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// Emit the register enum value for each RegisterClass.
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// Emit the register enum value for each RegisterClass.
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for (unsigned I = 0, E = RegisterClasses.size(); I != E; ++I) {
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for (unsigned I = 0, E = RegisterClasses.size(); I != E; ++I) {
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if (I != 0) O << ",\n";
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if (I != 0) O << ",\n";
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O << " RC_" << RegisterClasses[I]->TheDef->getName();
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O << " RC_" << RegisterClasses[I]->getName();
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}
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}
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O << "\n };\n";
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O << "\n };\n";
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@ -732,7 +732,7 @@ void AsmWriterEmitter::EmitRegIsInRegClass(raw_ostream &O) {
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const CodeGenRegisterClass &RC = *RegisterClasses[I];
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const CodeGenRegisterClass &RC = *RegisterClasses[I];
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// Give the register class a legal C name if it's anonymous.
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.TheDef->getName();
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std::string Name = RC.getName();
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O << " case RC_" << Name << ":\n";
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O << " case RC_" << Name << ":\n";
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// Emit the register list now.
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// Emit the register list now.
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@ -256,7 +256,7 @@ struct TupleExpander : SetTheory::Expander {
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
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CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
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: TheDef(R), EnumValue(-1) {
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: TheDef(R), Name(R->getName()), EnumValue(-1) {
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// Rename anonymous register classes.
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// Rename anonymous register classes.
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if (R->getName().size() > 9 && R->getName()[9] == '.') {
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if (R->getName().size() > 9 && R->getName()[9] == '.') {
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static unsigned AnonCounter = 0;
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static unsigned AnonCounter = 0;
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@ -385,8 +385,11 @@ static int TopoOrderRC(const void *PA, const void *PB) {
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return A->getName() < B->getName();
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return A->getName() < B->getName();
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}
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}
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const std::string &CodeGenRegisterClass::getName() const {
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std::string CodeGenRegisterClass::getQualifiedName() const {
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return TheDef->getName();
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if (Namespace.empty())
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return getName();
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else
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return Namespace + "::" + getName();
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}
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}
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// Compute sub-classes of all register classes.
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// Compute sub-classes of all register classes.
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@ -93,8 +93,9 @@ namespace llvm {
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// List of super-classes, topologocally ordered to have the larger classes
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// List of super-classes, topologocally ordered to have the larger classes
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// first. This is the same as sorting by EnumValue.
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// first. This is the same as sorting by EnumValue.
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SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
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SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
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public:
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Record *TheDef;
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Record *TheDef;
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std::string Name;
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public:
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unsigned EnumValue;
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unsigned EnumValue;
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std::string Namespace;
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std::string Namespace;
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std::vector<MVT::SimpleValueType> VTs;
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std::vector<MVT::SimpleValueType> VTs;
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@ -106,7 +107,12 @@ namespace llvm {
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DenseMap<Record*,Record*> SubRegClasses;
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DenseMap<Record*,Record*> SubRegClasses;
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std::string AltOrderSelect;
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std::string AltOrderSelect;
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const std::string &getName() const;
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// Return the Record that defined this class, or NULL if the class was
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// created by TableGen.
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Record *getDef() const { return TheDef; }
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const std::string &getName() const { return Name; }
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std::string getQualifiedName() const;
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const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
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const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
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unsigned getNumValueTypes() const { return VTs.size(); }
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unsigned getNumValueTypes() const { return VTs.size(); }
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@ -371,10 +371,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = *RegisterClasses[rc];
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const CodeGenRegisterClass &RC = *RegisterClasses[rc];
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OS << " MCRegisterClass(";
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OS << " MCRegisterClass(" << RC.getQualifiedName() + "RegClassID" << ", "
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if (!RC.Namespace.empty())
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OS << RC.Namespace << "::";
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OS << RC.getName() + "RegClassID" << ", "
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<< '\"' << RC.getName() << "\", "
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<< '\"' << RC.getName() << "\", "
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<< RC.SpillSize/8 << ", "
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<< RC.SpillSize/8 << ", "
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<< RC.SpillAlignment/8 << ", "
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<< RC.SpillAlignment/8 << ", "
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@ -556,17 +553,13 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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SRC.at(idx-1) = i->second;
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SRC.at(idx-1) = i->second;
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// Find the register class number of i->second for SuperRegClassMap.
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// Find the register class number of i->second for SuperRegClassMap.
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for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
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const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second);
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const CodeGenRegisterClass &RC2 = *RegisterClasses[rc2];
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assert(RC2 && "Invalid register class in SubRegClasses");
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if (RC2.TheDef == i->second) {
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SuperRegClassMap[RC2->EnumValue].insert(rc);
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SuperRegClassMap[rc2].insert(rc);
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break;
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}
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}
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}
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}
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// Give the register class a legal C name if it's anonymous.
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.TheDef->getName();
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std::string Name = RC.getName();
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OS << " // " << Name
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OS << " // " << Name
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<< " Sub-register Classes...\n"
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<< " Sub-register Classes...\n"
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@ -589,7 +582,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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const CodeGenRegisterClass &RC = *RegisterClasses[rc];
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const CodeGenRegisterClass &RC = *RegisterClasses[rc];
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// Give the register class a legal C name if it's anonymous.
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.TheDef->getName();
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std::string Name = RC.getName();
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OS << " // " << Name
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OS << " // " << Name
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<< " Super-register Classes...\n"
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<< " Super-register Classes...\n"
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@ -605,7 +598,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
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const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
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if (!Empty)
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if (!Empty)
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OS << ", ";
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OS << ", ";
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OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
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OS << "&" << RC2.getQualifiedName() << "RegClass";
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Empty = false;
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Empty = false;
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}
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}
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}
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}
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@ -620,7 +613,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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const CodeGenRegisterClass &RC = *RegisterClasses[rc];
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const CodeGenRegisterClass &RC = *RegisterClasses[rc];
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// Give the register class a legal C name if it's anonymous.
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.TheDef->getName();
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std::string Name = RC.getName();
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OS << " static const unsigned " << Name << "SubclassMask[] = { ";
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OS << " static const unsigned " << Name << "SubclassMask[] = { ";
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printBitVectorAsHex(OS, RC.getSubClasses(), 32);
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printBitVectorAsHex(OS, RC.getSubClasses(), 32);
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@ -639,7 +632,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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OS << " static const TargetRegisterClass* const "
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OS << " static const TargetRegisterClass* const "
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<< RC.getName() << "Superclasses[] = {\n";
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<< RC.getName() << "Superclasses[] = {\n";
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for (unsigned i = 0; i != Supers.size(); ++i)
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for (unsigned i = 0; i != Supers.size(); ++i)
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OS << " &" << getQualifiedName(Supers[i]->TheDef) << "RegClass,\n";
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OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
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OS << " NULL\n };\n\n";
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OS << " NULL\n };\n\n";
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}
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}
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@ -675,10 +668,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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OS << " };\n";
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OS << " };\n";
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}
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}
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OS << " const MCRegisterClass &MCR = " << Target.getName()
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OS << " const MCRegisterClass &MCR = " << Target.getName()
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<< "MCRegisterClasses[";
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<< "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];"
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if (!RC.Namespace.empty())
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OS << RC.Namespace << "::";
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OS << RC.getName() + "RegClassID];"
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<< " static const ArrayRef<unsigned> Order[] = {\n"
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<< " static const ArrayRef<unsigned> Order[] = {\n"
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<< " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
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<< " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
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for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
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for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
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@ -695,7 +685,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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OS << "\nnamespace {\n";
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OS << "\nnamespace {\n";
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OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
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OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
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OS << " &" << getQualifiedName(RegisterClasses[i]->TheDef)
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OS << " &" << RegisterClasses[i]->getQualifiedName()
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<< "RegClass,\n";
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<< "RegClass,\n";
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OS << " };\n";
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OS << " };\n";
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OS << "}\n"; // End of anonymous namespace...
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OS << "}\n"; // End of anonymous namespace...
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