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ExecutionDepsFix refactoring:
- Changing LiveRegs to be a vector This is the one of multiple patches that fix bugzilla https://bugs.llvm.org/show_bug.cgi?id=33869 Most of the patches are intended at refactoring the existent code. Additional relevant reviews: https://reviews.llvm.org/D40330 https://reviews.llvm.org/D40332 https://reviews.llvm.org/D40333 https://reviews.llvm.org/D40334 Differential Revision: https://reviews.llvm.org/D40331 Change-Id: I9cdd364bd7bf2a0bf61ea41a48d4bd310ec3bce4 llvm-svn: 323090
This commit is contained in:
Marina Yatsina
parent
dc43861508
commit
c52c77174c
@ -174,12 +174,13 @@ private:
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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unsigned NumRegUnits;
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LiveReg *LiveRegs;
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using LiveRegsDefInfo = std::vector<LiveReg>;
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LiveRegsDefInfo LiveRegs;
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// Keeps clearance information for all registers. Note that this
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// is different from the usual definition notion of liveness. The CPU
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// doesn't care whether or not we consider a register killed.
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using OutRegsInfoMap = SmallVector<LiveReg *, 4>;
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using OutRegsInfoMap = SmallVector<LiveRegsDefInfo, 4>;
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OutRegsInfoMap MBBOutRegsInfos;
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/// Current instruction number.
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@ -245,11 +246,12 @@ class ExecutionDomainFix : public MachineFunctionPass {
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const TargetRegisterInfo *TRI;
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std::vector<SmallVector<int, 1>> AliasMap;
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const unsigned NumRegs;
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LiveReg *LiveRegs;
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using LiveRegsDVInfo = std::vector<LiveReg>;
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LiveRegsDVInfo LiveRegs;
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// Keeps domain information for all registers. Note that this
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// is different from the usual definition notion of liveness. The CPU
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// doesn't care whether or not we consider a register killed.
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using OutRegsInfoMap = SmallVector<LiveReg *, 4>;
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using OutRegsInfoMap = SmallVector<LiveRegsDVInfo, 4>;
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OutRegsInfoMap MBBOutRegsInfos;
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ReachingDefAnalysis *RDA;
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@ -88,7 +88,7 @@ DomainValue *ExecutionDomainFix::resolve(DomainValue *&DVRef) {
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/// Set LiveRegs[rx] = dv, updating reference counts.
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void ExecutionDomainFix::setLiveReg(int rx, DomainValue *dv) {
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assert(unsigned(rx) < NumRegs && "Invalid index");
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assert(LiveRegs && "Must enter basic block first.");
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assert(!LiveRegs.empty() && "Must enter basic block first.");
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if (LiveRegs[rx].Value == dv)
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return;
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@ -100,7 +100,7 @@ void ExecutionDomainFix::setLiveReg(int rx, DomainValue *dv) {
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// Kill register rx, recycle or collapse any DomainValue.
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void ExecutionDomainFix::kill(int rx) {
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assert(unsigned(rx) < NumRegs && "Invalid index");
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assert(LiveRegs && "Must enter basic block first.");
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assert(!LiveRegs.empty() && "Must enter basic block first.");
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if (!LiveRegs[rx].Value)
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return;
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@ -111,7 +111,7 @@ void ExecutionDomainFix::kill(int rx) {
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/// Force register rx into domain.
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void ExecutionDomainFix::force(int rx, unsigned domain) {
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assert(unsigned(rx) < NumRegs && "Invalid index");
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assert(LiveRegs && "Must enter basic block first.");
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assert(!LiveRegs.empty() && "Must enter basic block first.");
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if (DomainValue *dv = LiveRegs[rx].Value) {
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if (dv->isCollapsed())
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dv->addDomain(domain);
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@ -141,7 +141,7 @@ void ExecutionDomainFix::collapse(DomainValue *dv, unsigned domain) {
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dv->setSingleDomain(domain);
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// If there are multiple users, give them new, unique DomainValues.
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if (LiveRegs && dv->Refs > 1)
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if (!LiveRegs.empty() && dv->Refs > 1)
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for (unsigned rx = 0; rx != NumRegs; ++rx)
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if (LiveRegs[rx].Value == dv)
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setLiveReg(rx, alloc(domain));
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@ -166,7 +166,7 @@ bool ExecutionDomainFix::merge(DomainValue *A, DomainValue *B) {
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B->Next = retain(A);
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for (unsigned rx = 0; rx != NumRegs; ++rx) {
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assert(LiveRegs && "no space allocated for live registers");
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assert(!LiveRegs.empty() && "no space allocated for live registers");
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if (LiveRegs[rx].Value == B)
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setLiveReg(rx, A);
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}
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@ -186,11 +186,11 @@ void ReachingDefAnalysis::enterBasicBlock(
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CurInstr = 0;
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// Set up LiveRegs to represent registers entering MBB.
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if (!LiveRegs)
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LiveRegs = new LiveReg[NumRegUnits];
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if (LiveRegs.empty())
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LiveRegs.resize(NumRegUnits);
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for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit) {
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LiveRegs[Unit].Def = ReachingDedDefaultVal;
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for (LiveReg &LiveRegDef : LiveRegs) {
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LiveRegDef.Def = ReachingDedDefaultVal;
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}
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// This is the entry block.
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@ -212,10 +212,10 @@ void ReachingDefAnalysis::enterBasicBlock(
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for (MachineBasicBlock* pred : MBB->predecessors()) {
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assert(pred->getNumber() < MBBOutRegsInfos.size() &&
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"Should have pre-allocated MBBInfos for all MBBs");
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LiveReg *Incoming = MBBOutRegsInfos[pred->getNumber()];
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const LiveRegsDefInfo& Incoming = MBBOutRegsInfos[pred->getNumber()];
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// Incoming is null if this is a backedge from a BB
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// we haven't processed yet
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if (Incoming == nullptr)
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if (Incoming.empty())
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continue;
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for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit) {
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@ -238,11 +238,11 @@ void ExecutionDomainFix::enterBasicBlock(
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MachineBasicBlock *MBB = TraversedMBB.MBB;
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// Set up LiveRegs to represent registers entering MBB.
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if (!LiveRegs)
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LiveRegs = new LiveReg[NumRegs];
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if (LiveRegs.empty())
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LiveRegs.resize(NumRegs);
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for (unsigned rx = 0; rx != NumRegs; ++rx) {
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LiveRegs[rx].Value = nullptr;
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for (LiveReg &LiveRegDef : LiveRegs) {
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LiveRegDef.Value = nullptr;
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}
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// This is the entry block.
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@ -255,10 +255,10 @@ void ExecutionDomainFix::enterBasicBlock(
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for (MachineBasicBlock* pred : MBB->predecessors()) {
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assert(pred->getNumber() < MBBOutRegsInfos.size() &&
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"Should have pre-allocated MBBInfos for all MBBs");
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LiveReg *Incoming = MBBOutRegsInfos[pred->getNumber()];
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LiveRegsDVInfo& Incoming = MBBOutRegsInfos[pred->getNumber()];
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// Incoming is null if this is a backedge from a BB
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// we haven't processed yet
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if (Incoming == nullptr)
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if (Incoming.empty())
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continue;
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for (unsigned rx = 0; rx != NumRegs; ++rx) {
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@ -293,7 +293,7 @@ void ExecutionDomainFix::enterBasicBlock(
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void ReachingDefAnalysis::leaveBasicBlock(
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const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
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assert(LiveRegs && "Must enter basic block first.");
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assert(!LiveRegs.empty() && "Must enter basic block first.");
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int MBBNumber = TraversedMBB.MBB->getNumber();
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assert(MBBNumber < MBBOutRegsInfos.size() && "Unexpected basic block number.");
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// Save register clearances at end of MBB - used by enterBasicBlock().
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@ -303,27 +303,24 @@ void ReachingDefAnalysis::leaveBasicBlock(
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// of the basic block for convenience. However, future use of this information
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// only cares about the clearance from the end of the block, so adjust
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// everything to be relative to the end of the basic block.
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for (unsigned i = 0, e = NumRegUnits; i != e; ++i)
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LiveRegs[i].Def -= CurInstr;
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LiveRegs = nullptr;
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for (LiveReg &OutLiveReg : MBBOutRegsInfos[MBBNumber])
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OutLiveReg.Def -= CurInstr;
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LiveRegs.clear();
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}
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void ExecutionDomainFix::leaveBasicBlock(
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const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
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assert(LiveRegs && "Must enter basic block first.");
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assert(!LiveRegs.empty() && "Must enter basic block first.");
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int MBBNumber = TraversedMBB.MBB->getNumber();
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assert(MBBNumber < MBBOutRegsInfos.size() && "Unexpected basic block number.");
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LiveReg *OldOutRegs = MBBOutRegsInfos[MBBNumber];
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LiveRegsDVInfo OldOutRegs = MBBOutRegsInfos[MBBNumber];
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// Save register clearances at end of MBB - used by enterBasicBlock().
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MBBOutRegsInfos[MBBNumber] = LiveRegs;
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if (OldOutRegs) {
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// This must be the second pass.
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// Release all the DomainValues instead of keeping them.
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for (unsigned i = 0, e = NumRegs; i != e; ++i)
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release(OldOutRegs[i].Value);
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delete[] OldOutRegs;
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for (LiveReg &OldLiveReg : OldOutRegs) {
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release(OldLiveReg.Value);
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}
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LiveRegs = nullptr;
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OldOutRegs.clear();
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LiveRegs.clear();
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}
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bool ExecutionDomainFix::visitInstr(MachineInstr *MI) {
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@ -574,7 +571,7 @@ void ExecutionDomainFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
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// Scan the explicit use operands for incoming domains.
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SmallVector<int, 4> used;
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if (LiveRegs)
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if (!LiveRegs.empty())
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for (unsigned i = mi->getDesc().getNumDefs(),
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e = mi->getDesc().getNumOperands(); i != e; ++i) {
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MachineOperand &mo = mi->getOperand(i);
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@ -613,7 +610,7 @@ void ExecutionDomainFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
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// incoming DomainValues that we want to merge.
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SmallVector<const LiveReg *, 4> Regs;
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for (int rx : used) {
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assert(LiveRegs && "no space allocated for live registers");
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assert(!LiveRegs.empty() && "no space allocated for live registers");
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LiveReg &LR = LiveRegs[rx];
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LR.Def = RDA->getReachingDef(mi, RC->getRegister(rx));
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// This useless DomainValue could have been missed above.
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@ -650,7 +647,7 @@ void ExecutionDomainFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
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// If latest didn't merge, it is useless now. Kill all registers using it.
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for (int i : used) {
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assert(LiveRegs && "no space allocated for live registers");
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assert(!LiveRegs.empty() && "no space allocated for live registers");
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if (LiveRegs[i].Value == Latest)
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kill(i);
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}
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@ -813,7 +810,7 @@ bool ExecutionDomainFix::runOnMachineFunction(MachineFunction &mf) {
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MF = &mf;
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TII = MF->getSubtarget().getInstrInfo();
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TRI = MF->getSubtarget().getRegisterInfo();
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LiveRegs = nullptr;
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LiveRegs.clear();
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assert(NumRegs == RC->getNumRegs() && "Bad regclass");
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DEBUG(dbgs() << "********** FIX EXECUTION DOMAIN: "
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@ -845,7 +842,7 @@ bool ExecutionDomainFix::runOnMachineFunction(MachineFunction &mf) {
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}
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// Initialize the MBBOutRegsInfos
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MBBOutRegsInfos.assign(mf.getNumBlockIDs(), nullptr);
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MBBOutRegsInfos.resize(mf.getNumBlockIDs());
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// Traverse the basic blocks.
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LoopTraversal Traversal;
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@ -854,13 +851,11 @@ bool ExecutionDomainFix::runOnMachineFunction(MachineFunction &mf) {
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processBasicBlock(TraversedMBB);
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}
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for (auto MBBOutRegs : MBBOutRegsInfos) {
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if (!MBBOutRegs)
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continue;
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for (unsigned i = 0, e = NumRegs; i != e; ++i)
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if (MBBOutRegs[i].Value)
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release(MBBOutRegs[i].Value);
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delete[] MBBOutRegs;
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for (LiveRegsDVInfo OutLiveRegs: MBBOutRegsInfos) {
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for (LiveReg OutLiveReg : OutLiveRegs) {
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if (OutLiveReg.Value)
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release(OutLiveReg.Value);
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}
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}
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MBBOutRegsInfos.clear();
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Avail.clear();
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@ -876,7 +871,7 @@ bool ReachingDefAnalysis::runOnMachineFunction(MachineFunction &mf) {
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TII = MF->getSubtarget().getInstrInfo();
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TRI = MF->getSubtarget().getRegisterInfo();
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LiveRegs = nullptr;
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LiveRegs.clear();
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NumRegUnits = TRI->getNumRegUnits();
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MBBReachingDefs.resize(mf.getNumBlockIDs());
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@ -884,7 +879,7 @@ bool ReachingDefAnalysis::runOnMachineFunction(MachineFunction &mf) {
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DEBUG(dbgs() << "********** REACHING DEFINITION ANALYSIS **********\n");
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// Initialize the MBBOutRegsInfos
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MBBOutRegsInfos.assign(mf.getNumBlockIDs(), nullptr);
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MBBOutRegsInfos.resize(mf.getNumBlockIDs());
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// Traverse the basic blocks.
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LoopTraversal Traversal;
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@ -903,12 +898,7 @@ bool ReachingDefAnalysis::runOnMachineFunction(MachineFunction &mf) {
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}
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void ReachingDefAnalysis::releaseMemory() {
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// Clear the LiveOuts vectors and collapse any remaining DomainValues.
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for (auto MBBOutRegs : MBBOutRegsInfos) {
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if (!MBBOutRegs)
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continue;
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delete[] MBBOutRegs;
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}
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// Clear the internal vectors.
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MBBOutRegsInfos.clear();
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MBBReachingDefs.clear();
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InstIds.clear();
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