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[SelectionDAG] Provide adequate register class for RegisterSDNode

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When adding operands to machine instructions in case of
RegisterSDNodes, generate a COPY node in case the register class
does not match the one in the instruction definition.

Differental Revision: https://reviews.llvm.org/D35561

llvm-svn: 324733
This commit is contained in:
Stefan Maksimovic 2018-02-09 13:55:25 +00:00
parent dd504a4274
commit c580e79901
3 changed files with 36 additions and 16 deletions
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17
lib/CodeGen/SelectionDAG/InstrEmitter.cpp
View File

@ -394,11 +394,26 @@ void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
} else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
MIB.addFPImm(F->getConstantFPValue());
} else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
unsigned VReg = R->getReg();
MVT OpVT = Op.getSimpleValueType();
const TargetRegisterClass *OpRC =
TLI->isTypeLegal(OpVT) ? TLI->getRegClassFor(OpVT) : nullptr;
const TargetRegisterClass *IIRC =
II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
: nullptr;
if (OpRC && IIRC && OpRC != IIRC &&
TargetRegisterInfo::isVirtualRegister(VReg)) {
unsigned NewVReg = MRI->createVirtualRegister(IIRC);
BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
VReg = NewVReg;
}
// Turn additional physreg operands into implicit uses on non-variadic
// instructions. This is used by call and return instructions passing
// arguments in registers.
bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
MIB.addReg(R->getReg(), getImplRegState(Imp));
MIB.addReg(VReg, getImplRegState(Imp));
} else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
MIB.addRegMask(RM->getRegMask());
} else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {

15
test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll
View File

@ -1,4 +1,5 @@
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | \
; RUN: FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}tgid_x:
; EG: MEM_RAT_CACHELESS STORE_RAW T1.X
@ -10,7 +11,8 @@ entry:
}
; FUNC-LABEL: {{^}}tgid_y:
; EG: MEM_RAT_CACHELESS STORE_RAW T1.Y
; EG: MEM_RAT_CACHELESS STORE_RAW [[REG:T[0-9]+]].X
; EG: MOV [[REG]].X, T1.Y
define amdgpu_kernel void @tgid_y(i32 addrspace(1)* %out) {
entry:
%0 = call i32 @llvm.r600.read.tgid.y() #0
@ -19,7 +21,8 @@ entry:
}
; FUNC-LABEL: {{^}}tgid_z:
; EG: MEM_RAT_CACHELESS STORE_RAW T1.Z
; EG: MEM_RAT_CACHELESS STORE_RAW [[REG:T[0-9]+]].X
; EG: MOV [[REG]].X, T1.Z
define amdgpu_kernel void @tgid_z(i32 addrspace(1)* %out) {
entry:
%0 = call i32 @llvm.r600.read.tgid.z() #0
@ -37,7 +40,8 @@ entry:
}
; FUNC-LABEL: {{^}}tidig_y:
; EG: MEM_RAT_CACHELESS STORE_RAW T0.Y
; EG: MEM_RAT_CACHELESS STORE_RAW [[REG:T[0-9]+]].X
; EG: MOV [[REG]].X, T0.Y
define amdgpu_kernel void @tidig_y(i32 addrspace(1)* %out) {
entry:
%0 = call i32 @llvm.r600.read.tidig.y() #0
@ -46,7 +50,8 @@ entry:
}
; FUNC-LABEL: {{^}}tidig_z:
; EG: MEM_RAT_CACHELESS STORE_RAW T0.Z
; EG: MEM_RAT_CACHELESS STORE_RAW [[REG:T[0-9]+]].X
; EG: MOV [[REG]].X, T0.Z
define amdgpu_kernel void @tidig_z(i32 addrspace(1)* %out) {
entry:
%0 = call i32 @llvm.r600.read.tidig.z() #0

20
test/CodeGen/Mips/tailcall/tailcall.ll
View File

@ -10,23 +10,23 @@
; RUN: -verify-machineinstrs -mips-tail-calls=1 < %s | \
; RUN: FileCheck %s -check-prefixes=ALL,PIC16
; RUN: llc -march=mipsel -relocation-model=pic -mattr=+micromips -mips-tail-calls=1 < %s | \
; RUN: FileCheck %s -check-prefixes=ALL,PIC32MM
; RUN: llc -march=mipsel -relocation-model=static -mattr=+micromips \
; RUN: llc -march=mipsel -relocation-model=pic -mattr=+micromips -verify-machineinstrs \
; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,PIC32MM
; RUN: llc -march=mipsel -relocation-model=static -mattr=+micromips -verify-machineinstrs \
; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32
; RUN: llc -march=mipsel -relocation-model=pic -mcpu=mips32r6 -mips-tail-calls=1 < %s | \
; RUN: FileCheck %s -check-prefixes=ALL,PIC32R6
; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r2 \
; RUN: llc -march=mipsel -relocation-model=pic -mcpu=mips32r6 -verify-machineinstrs \
; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,PIC32R6
; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r2 -verify-machineinstrs \
; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32
; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r2 \
; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r2 -verify-machineinstrs \
; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=PIC64
; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r6 \
; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r6 -verify-machineinstrs \
; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=STATIC64
; RUN: llc -march=mipsel -relocation-model=pic -mcpu=mips32r6 -mattr=+micromips \
; RUN: llc -march=mipsel -relocation-model=pic -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs \
; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,PIC32MM
; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \
; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 -verify-machineinstrs \
; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32MMR6
@g0 = common global i32 0, align 4