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Teach the x86 backend a couple tricks for dealing with v16i8 sra by a constant splat value. Fixes PR11289.

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llvm-svn: 143498
This commit is contained in:
Eli Friedman 2011-11-01 21:18:39 +00:00
parent 60742ecabb
commit c60a0ad611
2 changed files with 38 additions and 0 deletions
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18
lib/Target/X86/X86ISelLowering.cpp
View File

@ -966,6 +966,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::SRA, MVT::v4i32, Custom);
setOperationAction(ISD::SRA, MVT::v8i16, Custom);
setOperationAction(ISD::SRA, MVT::v16i8, Custom);
}
if (Subtarget->hasSSE42() || Subtarget->hasAVX())
@ -9994,6 +9995,23 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
R, DAG.getConstant(ShiftAmt, MVT::i32));
if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRA) {
if (ShiftAmt == 7) {
// R s>> 7 === R s< 0
SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl);
return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
}
// R s>> a === ((R u>> a) ^ m) - m
SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
MVT::i8));
SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
return Res;
}
}
}

20
test/CodeGen/X86/x86-shifts.ll
View File

@ -170,3 +170,23 @@ define <16 x i8> @shr9(<16 x i8> %A) nounwind {
; CHECK: pand
; CHECK: ret
}
define <16 x i8> @sra_v16i8_7(<16 x i8> %A) nounwind {
%B = ashr <16 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
ret <16 x i8> %B
; CHECK: sra_v16i8_7:
; CHECK: pxor
; CHECK: pcmpgtb
; CHECK: ret
}
define <16 x i8> @sra_v16i8(<16 x i8> %A) nounwind {
%B = ashr <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <16 x i8> %B
; CHECK: sra_v16i8:
; CHECK: psrlw $3
; CHECK: pand
; CHECK: pxor
; CHECK: psubb
; CHECK: ret
}