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Implement llvm.atomic.cmp.swap.i32 on PPC. Patch by Gary Benson!
llvm-svn: 53505
This commit is contained in:
Evan Cheng
parent
7457283357
commit
c69b53dff9
@ -40,8 +40,7 @@ cl::desc("enable preincrement load/store generation on PPC (experimental)"),
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cl::Hidden);
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PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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: TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()),
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PPCAtomicLabelIndex(0) {
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: TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
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setPow2DivIsCheap();
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@ -378,45 +377,47 @@ unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
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const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return 0;
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case PPCISD::FSEL: return "PPCISD::FSEL";
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case PPCISD::FCFID: return "PPCISD::FCFID";
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case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
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case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
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case PPCISD::STFIWX: return "PPCISD::STFIWX";
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case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
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case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
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case PPCISD::VPERM: return "PPCISD::VPERM";
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case PPCISD::Hi: return "PPCISD::Hi";
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case PPCISD::Lo: return "PPCISD::Lo";
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case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
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case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
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case PPCISD::SRL: return "PPCISD::SRL";
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case PPCISD::SRA: return "PPCISD::SRA";
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case PPCISD::SHL: return "PPCISD::SHL";
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case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
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case PPCISD::STD_32: return "PPCISD::STD_32";
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case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
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case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
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case PPCISD::MTCTR: return "PPCISD::MTCTR";
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case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
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case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
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case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
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case PPCISD::MFCR: return "PPCISD::MFCR";
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case PPCISD::VCMP: return "PPCISD::VCMP";
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case PPCISD::VCMPo: return "PPCISD::VCMPo";
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case PPCISD::LBRX: return "PPCISD::LBRX";
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case PPCISD::STBRX: return "PPCISD::STBRX";
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case PPCISD::LARX: return "PPCISD::LARX";
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case PPCISD::STCX: return "PPCISD::STCX";
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case PPCISD::CMP_UNRESERVE: return "PPCISD::CMP_UNRESERVE";
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case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
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case PPCISD::MFFS: return "PPCISD::MFFS";
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case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
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case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
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case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
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case PPCISD::MTFSF: return "PPCISD::MTFSF";
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case PPCISD::TAILCALL: return "PPCISD::TAILCALL";
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case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
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case PPCISD::FSEL: return "PPCISD::FSEL";
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case PPCISD::FCFID: return "PPCISD::FCFID";
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case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
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case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
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case PPCISD::STFIWX: return "PPCISD::STFIWX";
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case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
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case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
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case PPCISD::VPERM: return "PPCISD::VPERM";
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case PPCISD::Hi: return "PPCISD::Hi";
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case PPCISD::Lo: return "PPCISD::Lo";
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case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
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case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
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case PPCISD::SRL: return "PPCISD::SRL";
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case PPCISD::SRA: return "PPCISD::SRA";
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case PPCISD::SHL: return "PPCISD::SHL";
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case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
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case PPCISD::STD_32: return "PPCISD::STD_32";
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case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
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case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
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case PPCISD::MTCTR: return "PPCISD::MTCTR";
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case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
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case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
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case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
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case PPCISD::MFCR: return "PPCISD::MFCR";
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case PPCISD::VCMP: return "PPCISD::VCMP";
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case PPCISD::VCMPo: return "PPCISD::VCMPo";
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case PPCISD::LBRX: return "PPCISD::LBRX";
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case PPCISD::STBRX: return "PPCISD::STBRX";
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case PPCISD::ATOMIC_LOAD_ADD: return "PPCISD::ATOMIC_LOAD_ADD";
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case PPCISD::ATOMIC_CMP_SWAP: return "PPCISD::ATOMIC_CMP_SWAP";
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case PPCISD::ATOMIC_SWAP: return "PPCISD::ATOMIC_SWAP";
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case PPCISD::LARX: return "PPCISD::LARX";
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case PPCISD::STCX: return "PPCISD::STCX";
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case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
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case PPCISD::MFFS: return "PPCISD::MFFS";
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case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
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case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
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case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
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case PPCISD::MTFSF: return "PPCISD::MTFSF";
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case PPCISD::TAILCALL: return "PPCISD::TAILCALL";
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case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
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}
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}
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@ -2726,33 +2727,13 @@ SDOperand PPCTargetLowering::LowerAtomicLOAD_ADD(SDOperand Op, SelectionDAG &DAG
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SDOperand Ptr = Op.getOperand(1);
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SDOperand Incr = Op.getOperand(2);
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// Issue a "load and reserve".
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std::vector<MVT> VTs;
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VTs.push_back(VT);
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VTs.push_back(MVT::Other);
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SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32);
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SDVTList VTs = DAG.getVTList(VT, MVT::Other);
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SDOperand Ops[] = {
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Chain, // Chain
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Ptr, // Ptr
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Label, // Label
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Chain,
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Ptr,
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Incr,
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};
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SDOperand Load = DAG.getNode(PPCISD::LARX, VTs, Ops, 3);
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Chain = Load.getValue(1);
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// Compute new value.
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SDOperand NewVal = DAG.getNode(ISD::ADD, VT, Load, Incr);
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// Issue a "store and check".
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SDOperand Ops2[] = {
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Chain, // Chain
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NewVal, // Value
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Ptr, // Ptr
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Label, // Label
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};
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SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4);
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SDOperand OutOps[] = { Load, Store };
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return DAG.getMergeValues(OutOps, 2);
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return DAG.getNode(PPCISD::ATOMIC_LOAD_ADD, VTs, Ops, 3);
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}
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SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG) {
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@ -2762,39 +2743,14 @@ SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG
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SDOperand NewVal = Op.getOperand(2);
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SDOperand OldVal = Op.getOperand(3);
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// Issue a "load and reserve".
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std::vector<MVT> VTs;
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VTs.push_back(VT);
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VTs.push_back(MVT::Other);
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SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32);
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SDVTList VTs = DAG.getVTList(VT, MVT::Other);
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SDOperand Ops[] = {
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Chain, // Chain
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Ptr, // Ptr
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Label, // Label
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Chain,
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Ptr,
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OldVal,
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NewVal,
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};
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SDOperand Load = DAG.getNode(PPCISD::LARX, VTs, Ops, 3);
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Chain = Load.getValue(1);
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// Compare and unreserve if not equal.
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SDOperand Ops2[] = {
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Chain, // Chain
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OldVal, // Old value
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Load, // Value in memory
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Label, // Label
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};
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Chain = DAG.getNode(PPCISD::CMP_UNRESERVE, MVT::Other, Ops2, 4);
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// Issue a "store and check".
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SDOperand Ops3[] = {
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Chain, // Chain
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NewVal, // Value
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Ptr, // Ptr
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Label, // Label
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};
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SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops3, 4);
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SDOperand OutOps[] = { Load, Store };
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return DAG.getMergeValues(OutOps, 2);
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return DAG.getNode(PPCISD::ATOMIC_CMP_SWAP, VTs, Ops, 4);
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}
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SDOperand PPCTargetLowering::LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG) {
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@ -2803,30 +2759,13 @@ SDOperand PPCTargetLowering::LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Ptr = Op.getOperand(1);
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SDOperand NewVal = Op.getOperand(2);
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// Issue a "load and reserve".
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std::vector<MVT> VTs;
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VTs.push_back(VT);
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VTs.push_back(MVT::Other);
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SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32);
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SDVTList VTs = DAG.getVTList(VT, MVT::Other);
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SDOperand Ops[] = {
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Chain, // Chain
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Ptr, // Ptr
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Label, // Label
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Chain,
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Ptr,
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NewVal,
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};
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SDOperand Load = DAG.getNode(PPCISD::LARX, VTs, Ops, 3);
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Chain = Load.getValue(1);
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// Issue a "store and check".
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SDOperand Ops2[] = {
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Chain, // Chain
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NewVal, // Value
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Ptr, // Ptr
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Label, // Label
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};
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SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4);
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SDOperand OutOps[] = { Load, Store };
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return DAG.getMergeValues(OutOps, 2);
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return DAG.getNode(PPCISD::ATOMIC_SWAP, VTs, Ops, 3);
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}
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/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
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@ -3981,58 +3920,197 @@ MachineBasicBlock *
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PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) {
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
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MI->getOpcode() == PPC::SELECT_CC_I8 ||
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MI->getOpcode() == PPC::SELECT_CC_F4 ||
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MI->getOpcode() == PPC::SELECT_CC_F8 ||
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MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
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"Unexpected instr type to insert");
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// To "insert" a SELECT_CC instruction, we actually have to insert the diamond
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// control-flow pattern. The incoming instruction knows the destination vreg
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// to set, the condition code register to branch on, the true/false values to
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// select between, and a branch opcode to use.
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// To "insert" these instructions we actually have to insert their
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// control-flow patterns.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction::iterator It = BB;
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++It;
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// thisMBB:
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// ...
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// TrueVal = ...
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// cmpTY ccX, r1, r2
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// bCC copy1MBB
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// fallthrough --> copy0MBB
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MachineBasicBlock *thisMBB = BB;
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MachineFunction *F = BB->getParent();
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MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
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unsigned SelectPred = MI->getOperand(4).getImm();
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BuildMI(BB, TII->get(PPC::BCC))
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.addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
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F->insert(It, copy0MBB);
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F->insert(It, sinkMBB);
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// Update machine-CFG edges by transferring all successors of the current
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// block to the new block which will contain the Phi node for the select.
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sinkMBB->transferSuccessors(BB);
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// Next, add the true and fallthrough blocks as its successors.
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(sinkMBB);
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// copy0MBB:
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// %FalseValue = ...
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// # fallthrough to sinkMBB
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BB = copy0MBB;
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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// sinkMBB:
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
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// ...
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BB = sinkMBB;
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BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
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.addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
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.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
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if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
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MI->getOpcode() == PPC::SELECT_CC_I8 ||
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MI->getOpcode() == PPC::SELECT_CC_F4 ||
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MI->getOpcode() == PPC::SELECT_CC_F8 ||
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MI->getOpcode() == PPC::SELECT_CC_VRRC) {
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// The incoming instruction knows the destination vreg to set, the
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// condition code register to branch on, the true/false values to
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// select between, and a branch opcode to use.
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// thisMBB:
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// ...
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// TrueVal = ...
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// cmpTY ccX, r1, r2
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// bCC copy1MBB
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// fallthrough --> copy0MBB
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MachineBasicBlock *thisMBB = BB;
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MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
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unsigned SelectPred = MI->getOperand(4).getImm();
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BuildMI(BB, TII->get(PPC::BCC))
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.addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
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F->insert(It, copy0MBB);
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F->insert(It, sinkMBB);
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// Update machine-CFG edges by transferring all successors of the current
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// block to the new block which will contain the Phi node for the select.
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sinkMBB->transferSuccessors(BB);
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// Next, add the true and fallthrough blocks as its successors.
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(sinkMBB);
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// copy0MBB:
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// %FalseValue = ...
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// # fallthrough to sinkMBB
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BB = copy0MBB;
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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// sinkMBB:
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
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// ...
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BB = sinkMBB;
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BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
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.addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
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.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
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}
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else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32 ||
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MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) {
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bool is64bit = MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64;
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unsigned dest = MI->getOperand(0).getReg();
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unsigned ptrA = MI->getOperand(1).getReg();
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unsigned ptrB = MI->getOperand(2).getReg();
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unsigned incr = MI->getOperand(3).getReg();
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MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, loopMBB);
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F->insert(It, exitMBB);
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exitMBB->transferSuccessors(BB);
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MachineRegisterInfo &RegInfo = F->getRegInfo();
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unsigned TmpReg = RegInfo.createVirtualRegister(
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is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass :
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(const TargetRegisterClass *) &PPC::G8RCRegClass);
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// thisMBB:
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// ...
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// fallthrough --> loopMBB
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BB->addSuccessor(loopMBB);
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// loopMBB:
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// l[wd]arx dest, ptr
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// add r0, dest, incr
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// st[wd]cx. r0, ptr
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// bne- loopMBB
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// fallthrough --> exitMBB
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BB = loopMBB;
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BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
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.addReg(ptrA).addReg(ptrB);
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BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), TmpReg)
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.addReg(incr).addReg(dest);
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BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
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.addReg(TmpReg).addReg(ptrA).addReg(ptrB);
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BuildMI(BB, TII->get(PPC::BCC))
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.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
|
||||
BB->addSuccessor(loopMBB);
|
||||
BB->addSuccessor(exitMBB);
|
||||
|
||||
// exitMBB:
|
||||
// ...
|
||||
BB = exitMBB;
|
||||
}
|
||||
else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
|
||||
MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
|
||||
bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
|
||||
|
||||
unsigned dest = MI->getOperand(0).getReg();
|
||||
unsigned ptrA = MI->getOperand(1).getReg();
|
||||
unsigned ptrB = MI->getOperand(2).getReg();
|
||||
unsigned oldval = MI->getOperand(3).getReg();
|
||||
unsigned newval = MI->getOperand(4).getReg();
|
||||
|
||||
MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
||||
MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
||||
F->insert(It, loopMBB);
|
||||
F->insert(It, exitMBB);
|
||||
exitMBB->transferSuccessors(BB);
|
||||
|
||||
// thisMBB:
|
||||
// ...
|
||||
// fallthrough --> loopMBB
|
||||
BB->addSuccessor(loopMBB);
|
||||
|
||||
// loopMBB:
|
||||
// l[wd]arx dest, ptr
|
||||
// cmp[wd] dest, oldval
|
||||
// bne- exitMBB
|
||||
// st[wd]cx. newval, ptr
|
||||
// bne- loopMBB
|
||||
// fallthrough --> exitMBB
|
||||
BB = loopMBB;
|
||||
BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
|
||||
.addReg(ptrA).addReg(ptrB);
|
||||
BuildMI(BB, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
|
||||
.addReg(oldval).addReg(dest);
|
||||
BuildMI(BB, TII->get(PPC::BCC))
|
||||
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(exitMBB);
|
||||
BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
|
||||
.addReg(newval).addReg(ptrA).addReg(ptrB);
|
||||
BuildMI(BB, TII->get(PPC::BCC))
|
||||
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
|
||||
BB->addSuccessor(loopMBB);
|
||||
BB->addSuccessor(exitMBB);
|
||||
|
||||
// exitMBB:
|
||||
// ...
|
||||
BB = exitMBB;
|
||||
}
|
||||
else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32 ||
|
||||
MI->getOpcode() == PPC::ATOMIC_SWAP_I64) {
|
||||
bool is64bit = MI->getOpcode() == PPC::ATOMIC_SWAP_I64;
|
||||
|
||||
unsigned dest = MI->getOperand(0).getReg();
|
||||
unsigned ptrA = MI->getOperand(1).getReg();
|
||||
unsigned ptrB = MI->getOperand(2).getReg();
|
||||
unsigned newval = MI->getOperand(3).getReg();
|
||||
|
||||
MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
||||
MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
||||
F->insert(It, loopMBB);
|
||||
F->insert(It, exitMBB);
|
||||
exitMBB->transferSuccessors(BB);
|
||||
|
||||
// thisMBB:
|
||||
// ...
|
||||
// fallthrough --> loopMBB
|
||||
BB->addSuccessor(loopMBB);
|
||||
|
||||
// loopMBB:
|
||||
// l[wd]arx dest, ptr
|
||||
// st[wd]cx. newval, ptr
|
||||
// bne- loopMBB
|
||||
// fallthrough --> exitMBB
|
||||
BB = loopMBB;
|
||||
BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
|
||||
.addReg(ptrA).addReg(ptrB);
|
||||
BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
|
||||
.addReg(newval).addReg(ptrA).addReg(ptrB);
|
||||
BuildMI(BB, TII->get(PPC::BCC))
|
||||
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
|
||||
BB->addSuccessor(loopMBB);
|
||||
BB->addSuccessor(exitMBB);
|
||||
|
||||
// exitMBB:
|
||||
// ...
|
||||
BB = exitMBB;
|
||||
}
|
||||
else {
|
||||
assert(0 && "Unexpected instr type to insert");
|
||||
}
|
||||
|
||||
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
||||
return BB;
|
||||
|
||||
@ -152,6 +152,11 @@ namespace llvm {
|
||||
/// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
|
||||
MTFSF,
|
||||
|
||||
/// ATOMIC_LOAD_ADD, ATOMIC_CMP_SWAP, ATOMIC_SWAP - These
|
||||
/// correspond to the llvm.atomic.load.add, llvm.atomic.cmp.swap
|
||||
/// and llvm.atomic.swap intrinsics.
|
||||
ATOMIC_LOAD_ADD, ATOMIC_CMP_SWAP, ATOMIC_SWAP,
|
||||
|
||||
/// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
|
||||
/// reserve indexed. This is used to implement atomic operations.
|
||||
LARX,
|
||||
@ -160,10 +165,6 @@ namespace llvm {
|
||||
/// indexed. This is used to implement atomic operations.
|
||||
STCX,
|
||||
|
||||
/// CMP_UNRESERVE = Test for equality and "unreserve" if not true. This
|
||||
/// is used to implement atomic operations.
|
||||
CMP_UNRESERVE,
|
||||
|
||||
/// TAILCALL - Indicates a tail call should be taken.
|
||||
TAILCALL,
|
||||
/// TC_RETURN - A tail call return.
|
||||
@ -325,10 +326,6 @@ namespace llvm {
|
||||
SelectionDAG &DAG) const;
|
||||
|
||||
private:
|
||||
/// PPCAtomicLabelIndex - Keep track the number of PPC atomic labels.
|
||||
///
|
||||
unsigned PPCAtomicLabelIndex;
|
||||
|
||||
SDOperand getFramePointerFrameIndex(SelectionDAG & DAG) const;
|
||||
SDOperand getReturnAddrFrameIndex(SelectionDAG & DAG) const;
|
||||
|
||||
|
||||
@ -116,24 +116,35 @@ def : Pat<(PPCcall_ELF (i64 tglobaladdr:$dst)),
|
||||
def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)),
|
||||
(BL8_ELF texternalsym:$dst)>;
|
||||
|
||||
// Atomic operations.
|
||||
def LDARX : Pseudo<(outs G8RC:$rD), (ins memrr:$ptr, i32imm:$label),
|
||||
"\nLa${label}_entry:\n\tldarx $rD, $ptr",
|
||||
[(set G8RC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>;
|
||||
|
||||
let Defs = [CR0] in {
|
||||
def STDCX : Pseudo<(outs), (ins G8RC:$rS, memrr:$dst, i32imm:$label),
|
||||
"stdcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:",
|
||||
[(PPCstcx G8RC:$rS, xoaddr:$dst, imm:$label)]>;
|
||||
|
||||
def CMP_UNRESd : Pseudo<(outs), (ins G8RC:$rA, G8RC:$rB, i32imm:$label),
|
||||
"cmpd $rA, $rB\n\tbne- La${label}_exit",
|
||||
[(PPCcmp_unres G8RC:$rA, G8RC:$rB, imm:$label)]>;
|
||||
def CMP_UNRESdi : Pseudo<(outs), (ins G8RC:$rA, s16imm64:$imm, i32imm:$label),
|
||||
"cmpdi $rA, $imm\n\tbne- La${label}_exit",
|
||||
[(PPCcmp_unres G8RC:$rA, immSExt16:$imm, imm:$label)]>;
|
||||
// Atomic operations
|
||||
let usesCustomDAGSchedInserter = 1 in {
|
||||
let Uses = [CR0] in {
|
||||
def ATOMIC_LOAD_ADD_I64 : Pseudo<
|
||||
(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
|
||||
"${:comment} ATOMIC_LOAD_ADD_I64 PSEUDO!",
|
||||
[(set G8RC:$dst, (PPCatomic_load_add xoaddr:$ptr, G8RC:$incr))]>;
|
||||
def ATOMIC_CMP_SWAP_I64 : Pseudo<
|
||||
(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new),
|
||||
"${:comment} ATOMIC_CMP_SWAP_I64 PSEUDO!",
|
||||
[(set G8RC:$dst, (PPCatomic_cmp_swap xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
|
||||
def ATOMIC_SWAP_I64 : Pseudo<
|
||||
(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new),
|
||||
"${:comment} ATOMIC_SWAP_I64 PSEUDO!",
|
||||
[(set G8RC:$dst, (PPCatomic_swap xoaddr:$ptr, G8RC:$new))]>;
|
||||
}
|
||||
}
|
||||
|
||||
// Instructions to support atomic operations
|
||||
def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr),
|
||||
"ldarx $rD, $ptr", LdStLDARX,
|
||||
[(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>;
|
||||
|
||||
let Defs = [CR0] in
|
||||
def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst),
|
||||
"stdcx. $rS, $dst", LdStSTDCX,
|
||||
[(PPCstcx G8RC:$rS, xoaddr:$dst)]>,
|
||||
isDOT;
|
||||
|
||||
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
|
||||
def TCRETURNdi8 :Pseudo< (outs),
|
||||
(ins calltarget:$dst, i32imm:$offset, variable_ops),
|
||||
|
||||
@ -42,15 +42,21 @@ def SDT_PPCstbrx : SDTypeProfile<0, 4, [
|
||||
SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
|
||||
]>;
|
||||
|
||||
def SDT_PPCatomic_load_add : SDTypeProfile<1, 2, [
|
||||
SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>
|
||||
]>;
|
||||
def SDT_PPCatomic_cmp_swap : SDTypeProfile<1, 3, [
|
||||
SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>, SDTCisInt<3>
|
||||
]>;
|
||||
def SDT_PPCatomic_swap : SDTypeProfile<1, 2, [
|
||||
SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>
|
||||
]>;
|
||||
|
||||
def SDT_PPClarx : SDTypeProfile<1, 2, [
|
||||
SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>
|
||||
def SDT_PPClarx : SDTypeProfile<1, 1, [
|
||||
SDTCisInt<0>, SDTCisPtrTy<1>
|
||||
]>;
|
||||
def SDT_PPCstcx : SDTypeProfile<0, 3, [
|
||||
SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>
|
||||
]>;
|
||||
def SDT_PPCcmp_unres : SDTypeProfile<0, 3, [
|
||||
SDTCisSameAs<0, 1>, SDTCisInt<1>, SDTCisVT<2, i32>
|
||||
def SDT_PPCstcx : SDTypeProfile<0, 2, [
|
||||
SDTCisInt<0>, SDTCisPtrTy<1>
|
||||
]>;
|
||||
|
||||
def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
|
||||
@ -143,12 +149,22 @@ def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
|
||||
def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
|
||||
[SDNPHasChain, SDNPMayStore]>;
|
||||
|
||||
// Atomic operations
|
||||
def PPCatomic_load_add : SDNode<"PPCISD::ATOMIC_LOAD_ADD",
|
||||
SDT_PPCatomic_load_add,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
|
||||
def PPCatomic_cmp_swap : SDNode<"PPCISD::ATOMIC_CMP_SWAP",
|
||||
SDT_PPCatomic_cmp_swap,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
|
||||
def PPCatomic_swap : SDNode<"PPCISD::ATOMIC_SWAP",
|
||||
SDT_PPCatomic_swap,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
|
||||
|
||||
// Instructions to support atomic operations
|
||||
def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
|
||||
[SDNPHasChain, SDNPMayLoad]>;
|
||||
def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
|
||||
[SDNPHasChain, SDNPMayStore]>;
|
||||
def PPCcmp_unres : SDNode<"PPCISD::CMP_UNRESERVE", SDT_PPCcmp_unres,
|
||||
[SDNPHasChain]>;
|
||||
|
||||
// Instructions to support dynamic alloca.
|
||||
def SDTDynOp : SDTypeProfile<1, 2, []>;
|
||||
@ -530,24 +546,35 @@ def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
|
||||
"dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
|
||||
PPC970_DGroup_Single;
|
||||
|
||||
// Atomic operations.
|
||||
def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$ptr, i32imm:$label),
|
||||
"\nLa${label}_entry:\n\tlwarx $rD, $ptr", LdStLWARX,
|
||||
[(set GPRC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>;
|
||||
|
||||
let Defs = [CR0] in {
|
||||
def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label),
|
||||
"stwcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:",
|
||||
[(PPCstcx GPRC:$rS, xoaddr:$dst, imm:$label)]>;
|
||||
|
||||
def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm:$label),
|
||||
"cmpw $rA, $rB\n\tbne- La${label}_exit",
|
||||
[(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm:$label)]>;
|
||||
def CMP_UNRESwi : Pseudo<(outs), (ins GPRC:$rA, s16imm:$imm, i32imm:$label),
|
||||
"cmpwi $rA, $imm\n\tbne- La${label}_exit",
|
||||
[(PPCcmp_unres GPRC:$rA, immSExt16:$imm, imm:$label)]>;
|
||||
// Atomic operations
|
||||
let usesCustomDAGSchedInserter = 1 in {
|
||||
let Uses = [CR0] in {
|
||||
def ATOMIC_LOAD_ADD_I32 : Pseudo<
|
||||
(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
|
||||
"${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!",
|
||||
[(set GPRC:$dst, (PPCatomic_load_add xoaddr:$ptr, GPRC:$incr))]>;
|
||||
def ATOMIC_CMP_SWAP_I32 : Pseudo<
|
||||
(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
|
||||
"${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
|
||||
[(set GPRC:$dst, (PPCatomic_cmp_swap xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
|
||||
def ATOMIC_SWAP_I32 : Pseudo<
|
||||
(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
|
||||
"${:comment} ATOMIC_SWAP_I32 PSEUDO!",
|
||||
[(set GPRC:$dst, (PPCatomic_swap xoaddr:$ptr, GPRC:$new))]>;
|
||||
}
|
||||
}
|
||||
|
||||
// Instructions to support atomic operations
|
||||
def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
|
||||
"lwarx $rD, $src", LdStLWARX,
|
||||
[(set GPRC:$rD, (PPClarx xoaddr:$src))]>;
|
||||
|
||||
let Defs = [CR0] in
|
||||
def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
|
||||
"stwcx. $rS, $dst", LdStSTWCX,
|
||||
[(PPCstcx GPRC:$rS, xoaddr:$dst)]>,
|
||||
isDOT;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// PPC32 Load Instructions.
|
||||
//
|
||||
@ -1327,9 +1354,5 @@ def : Pat<(extloadf32 iaddr:$src),
|
||||
def : Pat<(extloadf32 xaddr:$src),
|
||||
(FMRSD (LFSX xaddr:$src))>;
|
||||
|
||||
// Atomic operations
|
||||
def : Pat<(PPCcmp_unres immSExt16:$imm, GPRC:$rA, imm:$label),
|
||||
(CMP_UNRESwi GPRC:$rA, immSExt16:$imm, imm:$label)>;
|
||||
|
||||
include "PPCInstrAltivec.td"
|
||||
include "PPCInstr64Bit.td"
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user