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Zap some redundant 'ori $?, $?, 0' from SPU.

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Also remove some code that died in the process.
One now non-existant ori is checked for.

llvm-svn: 115306
This commit is contained in:
Kalle Raiskila 2010-10-01 09:20:01 +00:00
parent 792e8112b0
commit c6bdc97934
3 changed files with 8 additions and 67 deletions
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70
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -111,55 +111,6 @@ namespace {
return false; return false;
} }
//===------------------------------------------------------------------===//
//! EVT to "useful stuff" mapping structure:
struct valtype_map_s {
EVT VT;
unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
bool ldresult_imm; /// LDRESULT instruction requires immediate?
unsigned lrinst; /// LR instruction
};
const valtype_map_s valtype_map[] = {
{ MVT::i8, SPU::ORBIr8, true, SPU::LRr8 },
{ MVT::i16, SPU::ORHIr16, true, SPU::LRr16 },
{ MVT::i32, SPU::ORIr32, true, SPU::LRr32 },
{ MVT::i64, SPU::ORr64, false, SPU::LRr64 },
{ MVT::f32, SPU::ORf32, false, SPU::LRf32 },
{ MVT::f64, SPU::ORf64, false, SPU::LRf64 },
// vector types... (sigh!)
{ MVT::v16i8, 0, false, SPU::LRv16i8 },
{ MVT::v8i16, 0, false, SPU::LRv8i16 },
{ MVT::v4i32, 0, false, SPU::LRv4i32 },
{ MVT::v2i64, 0, false, SPU::LRv2i64 },
{ MVT::v4f32, 0, false, SPU::LRv4f32 },
{ MVT::v2f64, 0, false, SPU::LRv2f64 }
};
const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
const valtype_map_s *getValueTypeMapEntry(EVT VT)
{
const valtype_map_s *retval = 0;
for (size_t i = 0; i < n_valtype_map; ++i) {
if (valtype_map[i].VT == VT) {
retval = valtype_map + i;
break;
}
}
#ifndef NDEBUG
if (retval == 0) {
report_fatal_error("SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns"
"NULL for " + Twine(VT.getEVTString()));
}
#endif
return retval;
}
//! Generate the carry-generate shuffle mask. //! Generate the carry-generate shuffle mask.
SDValue getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) { SDValue getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
SmallVector<SDValue, 16 > ShufBytes; SmallVector<SDValue, 16 > ShufBytes;
@ -882,23 +833,12 @@ SPUDAGToDAGISel::Select(SDNode *N) {
SDValue Arg = N->getOperand(0); SDValue Arg = N->getOperand(0);
SDValue Chain = N->getOperand(1); SDValue Chain = N->getOperand(1);
SDNode *Result; SDNode *Result;
const valtype_map_s *vtm = getValueTypeMapEntry(VT);
Result = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VT,
if (vtm->ldresult_ins == 0) { MVT::Other, Arg,
report_fatal_error("LDRESULT for unsupported type: " + getRC( VT.getSimpleVT()), Chain);
Twine(VT.getEVTString()));
}
Opc = vtm->ldresult_ins;
if (vtm->ldresult_imm) {
SDValue Zero = CurDAG->getTargetConstant(0, VT);
Result = CurDAG->getMachineNode(Opc, dl, VT, MVT::Other, Arg, Zero, Chain);
} else {
Result = CurDAG->getMachineNode(Opc, dl, VT, MVT::Other, Arg, Arg, Chain);
}
return Result; return Result;
} else if (Opc == SPUISD::IndirectAddr) { } else if (Opc == SPUISD::IndirectAddr) {
// Look at the operands: SelectCode() will catch the cases that aren't // Look at the operands: SelectCode() will catch the cases that aren't
// specifically handled here. // specifically handled here.

4
lib/Target/CellSPU/SPUInstrInfo.td
View File

@ -4355,7 +4355,7 @@ def : Pat<(i16 (anyext R8C:$rSrc)),
// anyext 8->32: Extend 8->32 bits, irrespective of sign, preserves high bits // anyext 8->32: Extend 8->32 bits, irrespective of sign, preserves high bits
def : Pat<(i32 (anyext R8C:$rSrc)), def : Pat<(i32 (anyext R8C:$rSrc)),
(ORIi8i32 R8C:$rSrc, 0)>; (COPY_TO_REGCLASS R8C:$rSrc, R32C)>;
// sext 16->64: Sign extend halfword to double word // sext 16->64: Sign extend halfword to double word
def : Pat<(sext_inreg R64C:$rSrc, i16), def : Pat<(sext_inreg R64C:$rSrc, i16),
@ -4379,7 +4379,7 @@ def : Pat<(i32 (zext (and R16C:$rSrc, 0xfff))),
// anyext 16->32: Extend 16->32 bits, irrespective of sign // anyext 16->32: Extend 16->32 bits, irrespective of sign
def : Pat<(i32 (anyext R16C:$rSrc)), def : Pat<(i32 (anyext R16C:$rSrc)),
(ORIi16i32 R16C:$rSrc, 0)>; (COPY_TO_REGCLASS R16C:$rSrc, R32C)>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Truncates: // Truncates:

1
test/CodeGen/CellSPU/arg_ret.ll
View File

@ -27,6 +27,7 @@ define ccc i32 @test_regs_and_stack( %paramstruct %prm, i32 %stackprm )
define ccc %paramstruct @test_return( i32 %param, %paramstruct %prm ) define ccc %paramstruct @test_return( i32 %param, %paramstruct %prm )
{ {
;CHECK: lqd $75, 80($sp) ;CHECK: lqd $75, 80($sp)
;CHECK-NOT: ori {{\$[0-9]+, \$[0-9]+, 0}}
;CHECK: lr $3, $4 ;CHECK: lr $3, $4
ret %paramstruct %prm ret %paramstruct %prm
} }