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correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics
llvm-svn: 91313
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@ -1579,7 +1579,7 @@ def Int_MemBarrierV7 : AInoP<(outs), (ins),
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Pseudo, NoItinerary,
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"dmb", "",
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[(ARMMemBarrier)]>,
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Requires<[HasV7]> {
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Requires<[IsARM, HasV7]> {
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let Inst{31-4} = 0xf57ff05;
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// FIXME: add support for options other than a full system DMB
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let Inst{3-0} = 0b1111;
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@ -1589,7 +1589,7 @@ def Int_SyncBarrierV7 : AInoP<(outs), (ins),
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Pseudo, NoItinerary,
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"dsb", "",
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[(ARMSyncBarrier)]>,
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Requires<[HasV7]> {
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Requires<[IsARM, HasV7]> {
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let Inst{31-4} = 0xf57ff04;
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// FIXME: add support for options other than a full system DSB
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let Inst{3-0} = 0b1111;
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@ -1073,14 +1073,16 @@ let hasSideEffects = 1 in {
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def t2Int_MemBarrierV7 : AInoP<(outs), (ins),
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Pseudo, NoItinerary,
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"dmb", "",
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[(ARMMemBarrier)]> {
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[(ARMMemBarrier)]>,
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Requires<[IsThumb2]> {
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// FIXME: add support for options other than a full system DMB
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}
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def t2Int_SyncBarrierV7 : AInoP<(outs), (ins),
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Pseudo, NoItinerary,
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"dsb", "",
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[(ARMSyncBarrier)]> {
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[(ARMSyncBarrier)]>,
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Requires<[IsThumb2]> {
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// FIXME: add support for options other than a full system DSB
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}
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}
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