Use the relationship models infrastructure to add two relations - getPredOpcode

and getPredNewOpcode. The first relates non predicated instructions with their
predicated forms and the second relates predicated instructions with their
predicate-new forms.

Patch by Jyotsna Verma!

llvm-svn: 167243
This commit is contained in:
Pranav Bhandarkar 2012-11-01 19:13:23 +00:00
parent efec4e2817
commit c796c7d713
3 changed files with 139 additions and 211 deletions

View File

@ -56,6 +56,16 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
bits<1> isPredicated = 0; bits<1> isPredicated = 0;
let TSFlags{6} = isPredicated; let TSFlags{6} = isPredicated;
// Dot new value store instructions.
bits<1> isNVStore = 0;
let TSFlags{8} = isNVStore;
// Fields used for relation models.
string BaseOpcode = "";
string CextOpcode = "";
string PredSense = "";
string PNewValue = "";
string InputType = ""; // Input is "imm" or "reg" type.
// *** The code above must match HexagonBaseInfo.h *** // *** The code above must match HexagonBaseInfo.h ***
} }

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@ -25,6 +25,7 @@
#include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/Support/MathExtras.h" #include "llvm/Support/MathExtras.h"
#define GET_INSTRINFO_CTOR #define GET_INSTRINFO_CTOR
#define GET_INSTRMAP_INFO
#include "HexagonGenInstrInfo.inc" #include "HexagonGenInstrInfo.inc"
#include "HexagonGenDFAPacketizer.inc" #include "HexagonGenDFAPacketizer.inc"
@ -1915,6 +1916,15 @@ unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
int HexagonInstrInfo:: int HexagonInstrInfo::
getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const { getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
enum Hexagon::PredSense inPredSense;
inPredSense = invertPredicate ? Hexagon::PredSense_false :
Hexagon::PredSense_true;
int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
if (CondOpcode >= 0) // Valid Conditional opcode/instruction
return CondOpcode;
// This switch case will be removed once all the instructions have been
// modified to use relation maps.
switch(Opc) { switch(Opc) {
case Hexagon::TFR: case Hexagon::TFR:
return !invertPredicate ? Hexagon::TFR_cPt : return !invertPredicate ? Hexagon::TFR_cPt :
@ -1934,24 +1944,6 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
case Hexagon::JMP_EQriPt_nv_V4: case Hexagon::JMP_EQriPt_nv_V4:
return !invertPredicate ? Hexagon::JMP_EQriPt_nv_V4 : return !invertPredicate ? Hexagon::JMP_EQriPt_nv_V4 :
Hexagon::JMP_EQriNotPt_nv_V4; Hexagon::JMP_EQriNotPt_nv_V4;
case Hexagon::ADD_ri:
return !invertPredicate ? Hexagon::ADD_ri_cPt :
Hexagon::ADD_ri_cNotPt;
case Hexagon::ADD_rr:
return !invertPredicate ? Hexagon::ADD_rr_cPt :
Hexagon::ADD_rr_cNotPt;
case Hexagon::XOR_rr:
return !invertPredicate ? Hexagon::XOR_rr_cPt :
Hexagon::XOR_rr_cNotPt;
case Hexagon::AND_rr:
return !invertPredicate ? Hexagon::AND_rr_cPt :
Hexagon::AND_rr_cNotPt;
case Hexagon::OR_rr:
return !invertPredicate ? Hexagon::OR_rr_cPt :
Hexagon::OR_rr_cNotPt;
case Hexagon::SUB_rr:
return !invertPredicate ? Hexagon::SUB_rr_cPt :
Hexagon::SUB_rr_cNotPt;
case Hexagon::COMBINE_rr: case Hexagon::COMBINE_rr:
return !invertPredicate ? Hexagon::COMBINE_rr_cPt : return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
Hexagon::COMBINE_rr_cNotPt; Hexagon::COMBINE_rr_cNotPt;

View File

@ -14,6 +14,18 @@
include "HexagonInstrFormats.td" include "HexagonInstrFormats.td"
include "HexagonImmediates.td" include "HexagonImmediates.td"
//===----------------------------------------------------------------------===//
// Classes used for relation maps.
//===----------------------------------------------------------------------===//
// PredRel - Filter class used to relate non-predicated instructions with their
// predicated forms.
class PredRel;
// PredNewRel - Filter class used to relate predicated instructions with their
// predicate-new forms.
class PredNewRel: PredRel;
// ImmRegRel - Filter class used to relate instructions having reg-reg form
// with their reg-imm counterparts.
class ImmRegRel;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Hexagon Instruction Predicate Definitions. // Hexagon Instruction Predicate Definitions.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -148,37 +160,91 @@ multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// ALU32/ALU + // ALU32/ALU (Instructions with register-register form)
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Add. multiclass ALU32_Pbase<string mnemonic, bit isNot,
let isCommutable = 1, isPredicable = 1 in bit isPredNew> {
def ADD_rr : ALU32_rr<(outs IntRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2),
"$dst = add($src1, $src2)",
[(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
(i32 IntRegs:$src2)))]>;
let isPredicable = 1 in let PNewValue = #!if(isPredNew, "new", "") in
def ADD_ri : ALU32_ri<(outs IntRegs:$dst), def #NAME# : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
") $dst = ")#mnemonic#"($src2, $src3)",
[]>;
}
multiclass ALU32_Pred<string mnemonic, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
defm _c#NAME# : ALU32_Pbase<mnemonic, PredNot, 0>;
// Predicate new
defm _cdn#NAME# : ALU32_Pbase<mnemonic, PredNot, 1>;
}
}
let InputType = "reg" in
multiclass ALU32_base<string mnemonic, string CextOp, SDNode OpNode> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_rr in {
let isPredicable = 1 in
def #NAME# : ALU32_rr<(outs IntRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2),
"$dst = "#mnemonic#"($src1, $src2)",
[(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
(i32 IntRegs:$src2)))]>;
let neverHasSideEffects = 1, isPredicated = 1 in {
defm Pt : ALU32_Pred<mnemonic, 0>;
defm NotPt : ALU32_Pred<mnemonic, 1>;
}
}
}
let isCommutable = 1 in {
defm ADD_rr : ALU32_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
defm AND_rr : ALU32_base<"and", "AND", and>, ImmRegRel, PredNewRel;
defm XOR_rr : ALU32_base<"xor", "XOR", xor>, ImmRegRel, PredNewRel;
defm OR_rr : ALU32_base<"or", "OR", or>, ImmRegRel, PredNewRel;
}
defm SUB_rr : ALU32_base<"sub", "SUB", sub>, ImmRegRel, PredNewRel;
//===----------------------------------------------------------------------===//
// ALU32/ALU (ADD with register-immediate form)
//===----------------------------------------------------------------------===//
multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
def #NAME# : ALU32_ri<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, s8Imm: $src3),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
") $dst = ")#mnemonic#"($src2, #$src3)",
[]>;
}
multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
defm _c#NAME# : ALU32ri_Pbase<mnemonic, PredNot, 0>;
// Predicate new
defm _cdn#NAME# : ALU32ri_Pbase<mnemonic, PredNot, 1>;
}
}
let InputType = "imm" in
multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
let isPredicable = 1 in
def #NAME# : ALU32_ri<(outs IntRegs:$dst),
(ins IntRegs:$src1, s16Imm:$src2), (ins IntRegs:$src1, s16Imm:$src2),
"$dst = add($src1, #$src2)", "$dst = "#mnemonic#"($src1, #$src2)",
[(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1), [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
s16ImmPred:$src2))]>; (s16ImmPred:$src2)))]>;
// Logical operations. let neverHasSideEffects = 1, isPredicated = 1 in {
let isPredicable = 1 in defm Pt : ALU32ri_Pred<mnemonic, 0>;
def XOR_rr : ALU32_rr<(outs IntRegs:$dst), defm NotPt : ALU32ri_Pred<mnemonic, 1>;
(ins IntRegs:$src1, IntRegs:$src2), }
"$dst = xor($src1, $src2)", }
[(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1), }
(i32 IntRegs:$src2)))]>;
let isCommutable = 1, isPredicable = 1 in defm ADD_ri : ALU32ri_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
def AND_rr : ALU32_rr<(outs IntRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2),
"$dst = and($src1, $src2)",
[(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
(i32 IntRegs:$src2)))]>;
def OR_ri : ALU32_ri<(outs IntRegs:$dst), def OR_ri : ALU32_ri<(outs IntRegs:$dst),
(ins IntRegs:$src1, s10Imm:$src2), (ins IntRegs:$src1, s10Imm:$src2),
@ -197,13 +263,6 @@ def AND_ri : ALU32_ri<(outs IntRegs:$dst),
[(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1), [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
s10ImmPred:$src2))]>; s10ImmPred:$src2))]>;
let isCommutable = 1, isPredicable = 1 in
def OR_rr : ALU32_rr<(outs IntRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2),
"$dst = or($src1, $src2)",
[(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
(i32 IntRegs:$src2)))]>;
// Negate. // Negate.
def NEG : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1), def NEG : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
"$dst = neg($src1)", "$dst = neg($src1)",
@ -214,14 +273,6 @@ def NOP : ALU32_rr<(outs), (ins),
"nop", "nop",
[]>; []>;
// Subtract.
let isPredicable = 1 in
def SUB_rr : ALU32_rr<(outs IntRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2),
"$dst = sub($src1, $src2)",
[(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
(i32 IntRegs:$src2)))]>;
// Rd32=sub(#s10,Rs32) // Rd32=sub(#s10,Rs32)
def SUB_ri : ALU32_ri<(outs IntRegs:$dst), def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
(ins s10Imm:$src1, IntRegs:$src2), (ins s10Imm:$src1, IntRegs:$src2),
@ -348,56 +399,6 @@ def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
// ALU32/PRED + // ALU32/PRED +
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Conditional add.
let neverHasSideEffects = 1, isPredicated = 1 in
def ADD_ri_cPt : ALU32_ri<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
"if ($src1) $dst = add($src2, #$src3)",
[]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def ADD_ri_cNotPt : ALU32_ri<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
"if (!$src1) $dst = add($src2, #$src3)",
[]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def ADD_ri_cdnPt : ALU32_ri<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
"if ($src1.new) $dst = add($src2, #$src3)",
[]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def ADD_ri_cdnNotPt : ALU32_ri<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
"if (!$src1.new) $dst = add($src2, #$src3)",
[]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def ADD_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if ($src1) $dst = add($src2, $src3)",
[]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def ADD_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if (!$src1) $dst = add($src2, $src3)",
[]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def ADD_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if ($src1.new) $dst = add($src2, $src3)",
[]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def ADD_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if (!$src1.new) $dst = add($src2, $src3)",
[]>;
// Conditional combine. // Conditional combine.
let neverHasSideEffects = 1, isPredicated = 1 in let neverHasSideEffects = 1, isPredicated = 1 in
@ -424,108 +425,6 @@ def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
"if (!$src1.new) $dst = combine($src2, $src3)", "if (!$src1.new) $dst = combine($src2, $src3)",
[]>; []>;
// Conditional logical operations.
let isPredicated = 1 in
def XOR_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if ($src1) $dst = xor($src2, $src3)",
[]>;
let isPredicated = 1 in
def XOR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if (!$src1) $dst = xor($src2, $src3)",
[]>;
let isPredicated = 1 in
def XOR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if ($src1.new) $dst = xor($src2, $src3)",
[]>;
let isPredicated = 1 in
def XOR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if (!$src1.new) $dst = xor($src2, $src3)",
[]>;
let isPredicated = 1 in
def AND_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if ($src1) $dst = and($src2, $src3)",
[]>;
let isPredicated = 1 in
def AND_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if (!$src1) $dst = and($src2, $src3)",
[]>;
let isPredicated = 1 in
def AND_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if ($src1.new) $dst = and($src2, $src3)",
[]>;
let isPredicated = 1 in
def AND_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if (!$src1.new) $dst = and($src2, $src3)",
[]>;
let isPredicated = 1 in
def OR_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if ($src1) $dst = or($src2, $src3)",
[]>;
let isPredicated = 1 in
def OR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if (!$src1) $dst = or($src2, $src3)",
[]>;
let isPredicated = 1 in
def OR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if ($src1.new) $dst = or($src2, $src3)",
[]>;
let isPredicated = 1 in
def OR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if (!$src1.new) $dst = or($src2, $src3)",
[]>;
// Conditional subtract.
let isPredicated = 1 in
def SUB_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if ($src1) $dst = sub($src2, $src3)",
[]>;
let isPredicated = 1 in
def SUB_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if (!$src1) $dst = sub($src2, $src3)",
[]>;
let isPredicated = 1 in
def SUB_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if ($src1.new) $dst = sub($src2, $src3)",
[]>;
let isPredicated = 1 in
def SUB_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
"if (!$src1.new) $dst = sub($src2, $src3)",
[]>;
// Conditional transfer. // Conditional transfer.
let neverHasSideEffects = 1, isPredicated = 1 in let neverHasSideEffects = 1, isPredicated = 1 in
def TFR_cPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), def TFR_cPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2),
@ -3546,4 +3445,31 @@ include "HexagonInstrInfoV5.td"
// V5 Instructions - // V5 Instructions -
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Generate mapping table to relate non-predicate instructions with their
// predicated formats - true and false.
//
def getPredOpcode : InstrMapping {
let FilterClass = "PredRel";
// Instructions with the same BaseOpcode and isNVStore values form a row.
let RowFields = ["BaseOpcode", "isNVStore", "PNewValue"];
// Instructions with the same predicate sense form a column.
let ColFields = ["PredSense"];
// The key column is the unpredicated instructions.
let KeyCol = [""];
// Value columns are PredSense=true and PredSense=false
let ValueCols = [["true"], ["false"]];
}
//===----------------------------------------------------------------------===//
// Generate mapping table to relate predicated instructions with their .new
// format.
//
def getPredNewOpcode : InstrMapping {
let FilterClass = "PredNewRel";
let RowFields = ["BaseOpcode", "PredSense", "isNVStore"];
let ColFields = ["PNewValue"];
let KeyCol = [""];
let ValueCols = [["new"]];
}