RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-21 03:05:15 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Refactor: Simplify boolean conditional return statements in lib/Target/PowerPC

Browse Source 
Summary: Use clang-tidy to simplify boolean conditional return statements

Reviewers: uweigand, rafael, wschmidt

Subscribers: craig.topper, llvm-commits

Patch by Richard Thomson!

Differential Revision: http://reviews.llvm.org/D9984

llvm-svn: 256493
This commit is contained in:
Alexander Kornienko 2015-12-28 13:38:42 +00:00
parent 3e8d6828a0
commit c882727d66
4 changed files with 4 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/Target/PowerPC/PPCFastISel.cpp
View File

@ -293,10 +293,7 @@ bool PPCFastISel::isValueAvailable(const Value *V) const {
return true;
const auto *I = cast<Instruction>(V);
if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
return true;
return false;
return FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB;
}
// Given a value Obj, create an Address object Addr that represents its

5
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -1612,10 +1612,7 @@ class BitPermutationSelector {
return false;
}
if (VRI.RLAmt != EffRLAmt)
return false;
return true;
return VRI.RLAmt == EffRLAmt;
};
for (auto &BG : BitGroups) {

4
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -11434,9 +11434,7 @@ bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
assert(Ty->isIntegerTy());
unsigned BitSize = Ty->getPrimitiveSizeInBits();
if (BitSize == 0 || BitSize > 64)
return false;
return true;
return !(BitSize == 0 || BitSize > 64);
}
bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {

4
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
View File

@ -164,9 +164,7 @@ private:
bool isRegInClass(unsigned Reg, const TargetRegisterClass *RC) {
if (TargetRegisterInfo::isVirtualRegister(Reg))
return RC->hasSubClassEq(MRI->getRegClass(Reg));
if (RC->contains(Reg))
return true;
return false;
return RC->contains(Reg);
}
// Return true iff the given register is a full vector register.