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MIPS DSP: ADDUH.QB instruction sub-class.
llvm-svn: 164840
This commit is contained in:
Akira Hatanaka
parent
d68cc7772f
commit
ca62e0c897
@ -141,6 +141,21 @@ class SHLL_QB_FMT<bits<5> op> : DSPInst {
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let Inst{5-0} = 0b010011;
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}
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// ADDUH.QB sub-class format.
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class ADDUH_QB_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b011000;
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}
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// DPA.W.PH sub-class format.
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class DPA_W_PH_FMT<bits<5> op> : DSPInst {
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bits<2> ac;
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@ -206,6 +206,22 @@ class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
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class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
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class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
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class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
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class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
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class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
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class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
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class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
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class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
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class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
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class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
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class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
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class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
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class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
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class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
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class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
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class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
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class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
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class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
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class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
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class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
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class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
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class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
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@ -325,6 +341,17 @@ class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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list<Register> Defs = [DSPCtrl];
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}
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class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin, RegisterClass RCD,
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RegisterClass RCS = RCD, RegisterClass RCT = RCD> {
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dag OutOperandList = (outs RCD:$rd);
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dag InOperandList = (ins RCS:$rs, RCT:$rt);
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string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
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list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
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InstrItinClass Itinerary = itin;
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list<Register> Defs = [DSPCtrl];
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}
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class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin> {
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dag OutOperandList = (outs CPURegs:$rt);
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@ -809,6 +836,48 @@ class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
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class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
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NoItinerary, DSPRegs, DSPRegs>;
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class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
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NoItinerary, DSPRegs>,
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ClearDefs, IsCommutable;
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class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
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NoItinerary, DSPRegs>,
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ClearDefs, IsCommutable;
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class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
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NoItinerary, DSPRegs>, ClearDefs;
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class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
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NoItinerary, DSPRegs>, ClearDefs;
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class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
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NoItinerary, DSPRegs>,
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ClearDefs, IsCommutable;
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class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
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NoItinerary, DSPRegs>,
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ClearDefs, IsCommutable;
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class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
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NoItinerary, DSPRegs>, ClearDefs;
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class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
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NoItinerary, DSPRegs>, ClearDefs;
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class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
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NoItinerary, CPURegs>,
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ClearDefs, IsCommutable;
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class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
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NoItinerary, CPURegs>,
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ClearDefs, IsCommutable;
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class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
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NoItinerary, CPURegs>, ClearDefs;
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class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
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NoItinerary, CPURegs>, ClearDefs;
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// Comparison
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class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
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int_mips_cmpgdu_eq_qb,
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@ -830,6 +899,18 @@ class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
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NoItinerary, DSPRegs>;
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// Multiplication
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class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", int_mips_mul_ph, NoItinerary,
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DSPRegs>, IsCommutable;
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class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
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NoItinerary, DSPRegs>, IsCommutable;
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class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
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NoItinerary, CPURegs>, IsCommutable;
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class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
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NoItinerary, CPURegs>, IsCommutable;
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class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
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NoItinerary, DSPRegs, DSPRegs>,
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IsCommutable;
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@ -1009,6 +1090,22 @@ def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
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def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
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def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
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def ABSQ_S_QB : ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
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def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC;
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def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
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def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC;
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def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
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def ADDQH_PH : ADDQH_PH_ENC, ADDQH_PH_DESC;
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def ADDQH_R_PH : ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
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def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC;
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def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
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def ADDQH_W : ADDQH_W_ENC, ADDQH_W_DESC;
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def ADDQH_R_W : ADDQH_R_W_ENC, ADDQH_R_W_DESC;
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def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC;
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def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC;
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def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
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def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
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def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
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def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
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def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
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def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC;
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def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
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@ -336,3 +336,203 @@ entry:
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}
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declare <4 x i8> @llvm.mips.absq.s.qb(<4 x i8>) nounwind
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define { i32 } @test__builtin_mips_mul_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: mul.ph
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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%2 = tail call <2 x i16> @llvm.mips.mul.ph(<2 x i16> %0, <2 x i16> %1)
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%3 = bitcast <2 x i16> %2 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
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ret { i32 } %.fca.0.insert
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}
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declare <2 x i16> @llvm.mips.mul.ph(<2 x i16>, <2 x i16>) nounwind
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define { i32 } @test__builtin_mips_mul_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: mul_s.ph
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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%2 = tail call <2 x i16> @llvm.mips.mul.s.ph(<2 x i16> %0, <2 x i16> %1)
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%3 = bitcast <2 x i16> %2 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
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ret { i32 } %.fca.0.insert
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}
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declare <2 x i16> @llvm.mips.mul.s.ph(<2 x i16>, <2 x i16>) nounwind
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define i32 @test__builtin_mips_mulq_rs_w1(i32 %i0, i32 %a0, i32 %a1) nounwind {
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entry:
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; CHECK: mulq_rs.w
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%0 = tail call i32 @llvm.mips.mulq.rs.w(i32 %a0, i32 %a1)
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ret i32 %0
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}
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declare i32 @llvm.mips.mulq.rs.w(i32, i32) nounwind
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define i32 @test__builtin_mips_mulq_s_w1(i32 %i0, i32 %a0, i32 %a1) nounwind {
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entry:
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; CHECK: mulq_s.w
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%0 = tail call i32 @llvm.mips.mulq.s.w(i32 %a0, i32 %a1)
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ret i32 %0
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}
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declare i32 @llvm.mips.mulq.s.w(i32, i32) nounwind
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define { i32 } @test__builtin_mips_adduh_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
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entry:
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; CHECK: adduh.qb
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%1 = bitcast i32 %a1.coerce to <4 x i8>
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%2 = tail call <4 x i8> @llvm.mips.adduh.qb(<4 x i8> %0, <4 x i8> %1)
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%3 = bitcast <4 x i8> %2 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
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ret { i32 } %.fca.0.insert
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}
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declare <4 x i8> @llvm.mips.adduh.qb(<4 x i8>, <4 x i8>) nounwind readnone
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define { i32 } @test__builtin_mips_adduh_r_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
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entry:
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; CHECK: adduh_r.qb
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%1 = bitcast i32 %a1.coerce to <4 x i8>
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%2 = tail call <4 x i8> @llvm.mips.adduh.r.qb(<4 x i8> %0, <4 x i8> %1)
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%3 = bitcast <4 x i8> %2 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
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ret { i32 } %.fca.0.insert
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}
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declare <4 x i8> @llvm.mips.adduh.r.qb(<4 x i8>, <4 x i8>) nounwind readnone
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define { i32 } @test__builtin_mips_subuh_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
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entry:
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; CHECK: subuh.qb
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%1 = bitcast i32 %a1.coerce to <4 x i8>
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%2 = tail call <4 x i8> @llvm.mips.subuh.qb(<4 x i8> %0, <4 x i8> %1)
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%3 = bitcast <4 x i8> %2 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
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ret { i32 } %.fca.0.insert
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}
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declare <4 x i8> @llvm.mips.subuh.qb(<4 x i8>, <4 x i8>) nounwind readnone
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define { i32 } @test__builtin_mips_subuh_r_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
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entry:
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; CHECK: subuh_r.qb
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%1 = bitcast i32 %a1.coerce to <4 x i8>
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%2 = tail call <4 x i8> @llvm.mips.subuh.r.qb(<4 x i8> %0, <4 x i8> %1)
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%3 = bitcast <4 x i8> %2 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
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ret { i32 } %.fca.0.insert
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}
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declare <4 x i8> @llvm.mips.subuh.r.qb(<4 x i8>, <4 x i8>) nounwind readnone
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define { i32 } @test__builtin_mips_addqh_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
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entry:
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; CHECK: addqh.ph
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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%2 = tail call <2 x i16> @llvm.mips.addqh.ph(<2 x i16> %0, <2 x i16> %1)
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%3 = bitcast <2 x i16> %2 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
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ret { i32 } %.fca.0.insert
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}
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declare <2 x i16> @llvm.mips.addqh.ph(<2 x i16>, <2 x i16>) nounwind readnone
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define { i32 } @test__builtin_mips_addqh_r_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
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entry:
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; CHECK: addqh_r.ph
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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%2 = tail call <2 x i16> @llvm.mips.addqh.r.ph(<2 x i16> %0, <2 x i16> %1)
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%3 = bitcast <2 x i16> %2 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
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ret { i32 } %.fca.0.insert
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}
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declare <2 x i16> @llvm.mips.addqh.r.ph(<2 x i16>, <2 x i16>) nounwind readnone
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define i32 @test__builtin_mips_addqh_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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entry:
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; CHECK: addqh.w
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%0 = tail call i32 @llvm.mips.addqh.w(i32 %a0, i32 %a1)
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ret i32 %0
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}
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declare i32 @llvm.mips.addqh.w(i32, i32) nounwind readnone
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define i32 @test__builtin_mips_addqh_r_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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entry:
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; CHECK: addqh_r.w
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%0 = tail call i32 @llvm.mips.addqh.r.w(i32 %a0, i32 %a1)
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ret i32 %0
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}
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declare i32 @llvm.mips.addqh.r.w(i32, i32) nounwind readnone
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define { i32 } @test__builtin_mips_subqh_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
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entry:
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; CHECK: subqh.ph
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%2 = tail call <2 x i16> @llvm.mips.subqh.ph(<2 x i16> %0, <2 x i16> %1)
|
||||
%3 = bitcast <2 x i16> %2 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.subqh.ph(<2 x i16>, <2 x i16>) nounwind readnone
|
||||
|
||||
define { i32 } @test__builtin_mips_subqh_r_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: subqh_r.ph
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%2 = tail call <2 x i16> @llvm.mips.subqh.r.ph(<2 x i16> %0, <2 x i16> %1)
|
||||
%3 = bitcast <2 x i16> %2 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.subqh.r.ph(<2 x i16>, <2 x i16>) nounwind readnone
|
||||
|
||||
define i32 @test__builtin_mips_subqh_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: subqh.w
|
||||
|
||||
%0 = tail call i32 @llvm.mips.subqh.w(i32 %a0, i32 %a1)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.mips.subqh.w(i32, i32) nounwind readnone
|
||||
|
||||
define i32 @test__builtin_mips_subqh_r_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: subqh_r.w
|
||||
|
||||
%0 = tail call i32 @llvm.mips.subqh.r.w(i32 %a0, i32 %a1)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.mips.subqh.r.w(i32, i32) nounwind readnone
|
||||
|
||||
Loading…
Reference in New Issue
Block a user