mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-11 14:16:59 +00:00
Hopefully fix the objdir != srcdir issue
llvm-svn: 9761
This commit is contained in:
parent
f9caf0045e
commit
ca7a346fce
@ -15,27 +15,33 @@ $(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
|
||||
X86GenRegisterInfo.inc X86GenInstrNames.inc \
|
||||
X86GenInstrInfo.inc X86GenInstrSelector.inc
|
||||
|
||||
X86GenRegisterNames.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
|
||||
X86GenRegisterNames.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \
|
||||
$(SourceDir)/../Target.td $(TBLGEN)
|
||||
@echo "Building X86.td register names with tblgen"
|
||||
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
|
||||
|
||||
X86GenRegisterInfo.h.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
|
||||
X86GenRegisterInfo.h.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \
|
||||
$(SourceDir)/../Target.td $(TBLGEN)
|
||||
@echo "Building X86.td register information header with tblgen"
|
||||
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
|
||||
|
||||
X86GenRegisterInfo.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
|
||||
X86GenRegisterInfo.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \
|
||||
$(SourceDir)/../Target.td $(TBLGEN)
|
||||
@echo "Building X86.td register information implementation with tblgen"
|
||||
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
|
||||
|
||||
X86GenInstrNames.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
|
||||
X86GenInstrNames.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \
|
||||
$(SourceDir)/../Target.td $(TBLGEN)
|
||||
@echo "Building X86.td instruction names with tblgen"
|
||||
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
|
||||
|
||||
X86GenInstrInfo.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
|
||||
X86GenInstrInfo.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \
|
||||
$(SourceDir)/../Target.td $(TBLGEN)
|
||||
@echo "Building X86.td instruction information with tblgen"
|
||||
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
|
||||
|
||||
X86GenInstrSelector.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
|
||||
X86GenInstrSelector.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \
|
||||
$(SourceDir)/../Target.td $(TBLGEN)
|
||||
@echo "Building X86.td instruction selector with tblgen"
|
||||
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
|
||||
|
||||
|
Loading…
x
Reference in New Issue
Block a user