RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-02-23 14:03:14 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

This testcase tests command line attributes which we don't yet support.

Browse Source 
In fact, we're probably going to support these flags in completely different
ways. So this test is no longer valid.

llvm-svn: 182899
This commit is contained in:
Bill Wendling 2013-05-30 00:32:04 +00:00
parent ecf5cbb5aa
commit cab3fa1f1c
1 changed files with 0 additions and 62 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

62
test/CodeGen/X86/subtarget-feature-change.ll
View File

@ -1,62 +0,0 @@
; RUN: llc < %s -march=x86-64 | FileCheck %s
; This should not generate SSE instructions:
;
; CHECK: without.sse:
; CHECK: flds
; CHECK: fmuls
; CHECK: fstps
define void @without.sse(float* nocapture %a, float* nocapture %b, float* nocapture %c, i32 %n) #0 {
entry:
%cmp9 = icmp sgt i32 %n, 0
br i1 %cmp9, label %for.body, label %for.end
for.body:
%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
%arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv
%0 = load float* %arrayidx, align 4
%arrayidx2 = getelementptr inbounds float* %c, i64 %indvars.iv
%1 = load float* %arrayidx2, align 4
%mul = fmul float %0, %1
%arrayidx4 = getelementptr inbounds float* %a, i64 %indvars.iv
store float %mul, float* %arrayidx4, align 4
%indvars.iv.next = add i64 %indvars.iv, 1
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
%exitcond = icmp eq i32 %lftr.wideiv, %n
br i1 %exitcond, label %for.end, label %for.body
for.end:
ret void
}
; This should generate SSE instructions:
;
; CHECK: with.sse
; CHECK: movss
; CHECK: mulss
; CHECK: movss
define void @with.sse(float* nocapture %a, float* nocapture %b, float* nocapture %c, i32 %n) #1 {
entry:
%cmp9 = icmp sgt i32 %n, 0
br i1 %cmp9, label %for.body, label %for.end
for.body:
%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
%arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv
%0 = load float* %arrayidx, align 4
%arrayidx2 = getelementptr inbounds float* %c, i64 %indvars.iv
%1 = load float* %arrayidx2, align 4
%mul = fmul float %0, %1
%arrayidx4 = getelementptr inbounds float* %a, i64 %indvars.iv
store float %mul, float* %arrayidx4, align 4
%indvars.iv.next = add i64 %indvars.iv, 1
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
%exitcond = icmp eq i32 %lftr.wideiv, %n
br i1 %exitcond, label %for.end, label %for.body
for.end:
ret void
}
attributes #0 = { nounwind optsize ssp uwtable "target-cpu"="core2" "target-features"="-sse4a,-avx2,-xop,-fma4,-bmi2,-3dnow,-3dnowa,-pclmul,-sse,-avx,-sse41,-ssse3,+mmx,-rtm,-sse42,-lzcnt,-f16c,-popcnt,-bmi,-aes,-fma,-rdrand,-sse2,-sse3" }
attributes #1 = { nounwind optsize ssp uwtable "target-cpu"="core2" "target-features"="-sse4a,-avx2,-xop,-fma4,-bmi2,-3dnow,-3dnowa,-pclmul,+sse,-avx,-sse41,+ssse3,+mmx,-rtm,-sse42,-lzcnt,-f16c,-popcnt,-bmi,-aes,-fma,-rdrand,+sse2,+sse3" }