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Add, to constant islands, long jumps similar to ARM far branch.

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llvm-svn: 195312
This commit is contained in:
Reed Kotler 2013-11-21 05:13:23 +00:00
parent 5480edb76f
commit caba86b795
3 changed files with 60 additions and 2 deletions
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1
lib/Target/Mips/Mips16InstrInfo.td
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@ -734,6 +734,7 @@ def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> {
let hasDelaySlot = 0; // not true, but we add the nop for now
let isCall=1;
let Defs = [RA];
}
//

24
lib/Target/Mips/MipsConstantIslandPass.cpp
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@ -1399,9 +1399,29 @@ bool
MipsConstantIslands::fixupUnconditionalBr(ImmBranch &Br) {
MachineInstr *MI = Br.MI;
MachineBasicBlock *MBB = MI->getParent();
MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
// Use BL to implement far jump.
Br.MaxDisp = ((1 << 16)-1) * 2;
MI->setDesc(TII->get(Mips::BimmX16));
unsigned BimmX16MaxDisp = ((1 << 16)-1) * 2;
if (isBBInRange(MI, DestBB, BimmX16MaxDisp)) {
Br.MaxDisp = BimmX16MaxDisp;
MI->setDesc(TII->get(Mips::BimmX16));
}
else {
// need to give the math a more careful look here
// this is really a segment address and not
// a PC relative address. FIXME. But I think that
// just reducing the bits by 1 as I've done is correct.
// The basic block we are branching too much be longword aligned.
// we know that RA is saved because we always save it right now.
// this requirement will be relaxed later but we also have an alternate
// way to implement this that I will implement that does not need jal.
// We should have a way to back out this alignment restriction if we "can" later.
// but it is not harmful.
//
DestBB->setAlignment(2);
Br.MaxDisp = ((1<<24)-1) * 2;
MI->setDesc(TII->get(Mips::Jal16));
}
BBInfo[MBB->getNumber()].Size += 2;
adjustBBOffsetsAfter(MBB);
HasFarJump = true;

37
test/CodeGen/Mips/mbrsize4a.ll Normal file
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@ -0,0 +1,37 @@
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands < %s | FileCheck %s -check-prefix=jal16
@j = global i32 10, align 4
@.str = private unnamed_addr constant [11 x i8] c"at bottom\0A\00", align 1
@i = common global i32 0, align 4
; Function Attrs: nounwind
define i32 @main() #0 {
entry:
%retval = alloca i32, align 4
store i32 0, i32* %retval
br label %z
z: ; preds = %y, %entry
%call = call i32 bitcast (i32 (...)* @foo to i32 ()*)()
call void asm sideeffect ".space 10000000", ""() #2, !srcloc !1
br label %y
y: ; preds = %z
%call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0))
br label %z
return: ; No predecessors!
%0 = load i32* %retval
ret i32 %0
; jal16: jal $BB{{[0-9]+}}_{{[0-9]+}}
}
declare i32 @foo(...) #1
declare i32 @printf(i8*, ...) #1
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #2 = { nounwind }
!1 = metadata !{i32 68}