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Wrap a long line and add some parens to be consistent.
llvm-svn: 98596
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@ -243,8 +243,9 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
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BaseKill = true; // New base is always killed right its use.
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}
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bool isDPR = Opcode == ARM::VLDRD || Opcode == ARM::VSTRD;
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bool isDef = isi32Load(Opcode) || Opcode == ARM::VLDRS || Opcode == ARM::VLDRD;
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bool isDPR = (Opcode == ARM::VLDRD || Opcode == ARM::VSTRD);
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bool isDef = (isi32Load(Opcode) || Opcode == ARM::VLDRS ||
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Opcode == ARM::VLDRD);
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Opcode = getLoadStoreMultipleOpcode(Opcode);
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MachineInstrBuilder MIB = (isAM4)
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? BuildMI(MBB, MBBI, dl, TII->get(Opcode))
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