Wrap a long line and add some parens to be consistent.

llvm-svn: 98596
This commit is contained in:
Bob Wilson 2010-03-16 00:31:15 +00:00
parent adff4d133f
commit cb28bed4f6

View File

@ -243,8 +243,9 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
BaseKill = true; // New base is always killed right its use.
}
bool isDPR = Opcode == ARM::VLDRD || Opcode == ARM::VSTRD;
bool isDef = isi32Load(Opcode) || Opcode == ARM::VLDRS || Opcode == ARM::VLDRD;
bool isDPR = (Opcode == ARM::VLDRD || Opcode == ARM::VSTRD);
bool isDef = (isi32Load(Opcode) || Opcode == ARM::VLDRS ||
Opcode == ARM::VLDRD);
Opcode = getLoadStoreMultipleOpcode(Opcode);
MachineInstrBuilder MIB = (isAM4)
? BuildMI(MBB, MBBI, dl, TII->get(Opcode))