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All callee-saved registers are live-out of a return block.
llvm-svn: 83223
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@ -313,8 +313,10 @@ void SchedulePostRATDList::StartBlock(MachineBasicBlock *BB) {
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// Clear "do not change" set.
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KeepRegs.clear();
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bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn());
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// Determine the live-out physregs for this block.
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if (!BB->empty() && BB->back().getDesc().isReturn()) {
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if (IsReturnBlock) {
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// In a return block, examine the function live-out regs.
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for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
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E = MRI.liveout_end(); I != E; ++I) {
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@ -348,24 +350,25 @@ void SchedulePostRATDList::StartBlock(MachineBasicBlock *BB) {
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DefIndices[AliasReg] = ~0u;
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}
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}
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}
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// Also mark as live-out any callee-saved registers that were not
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// saved in the prolog.
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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BitVector Pristine = MFI->getPristineRegs(BB);
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for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
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unsigned Reg = *I;
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if (!Pristine.test(Reg)) continue;
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[Reg] = BB->size();
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DefIndices[Reg] = ~0u;
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// Repeat, for all aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[AliasReg] = BB->size();
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DefIndices[AliasReg] = ~0u;
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}
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// Mark live-out callee-saved registers. In a return block this is
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// all callee-saved registers. In non-return this is any
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// callee-saved register that is not saved in the prolog.
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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BitVector Pristine = MFI->getPristineRegs(BB);
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for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
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unsigned Reg = *I;
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if (!IsReturnBlock && !Pristine.test(Reg)) continue;
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[Reg] = BB->size();
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DefIndices[Reg] = ~0u;
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// Repeat, for all aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[AliasReg] = BB->size();
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DefIndices[AliasReg] = ~0u;
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}
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}
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}
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