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[AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VI
See bug 32621: https://bugs.llvm.org//show_bug.cgi?id=32621 Reviewers: vpykhtin, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D35902 llvm-svn: 310251
This commit is contained in:
Dmitry Preobrazhensky
parent
a7f75ee70d
commit
cbaa1074ef
@ -164,7 +164,8 @@ public:
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ImmTyOpSelHi,
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ImmTyNegLo,
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ImmTyNegHi,
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ImmTySwizzle
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ImmTySwizzle,
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ImmTyHigh
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};
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struct TokOp {
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@ -312,6 +313,7 @@ public:
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bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); }
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bool isNegLo() const { return isImmTy(ImmTyNegLo); }
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bool isNegHi() const { return isImmTy(ImmTyNegHi); }
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bool isHigh() const { return isImmTy(ImmTyHigh); }
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bool isMod() const {
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return isClampSI() || isOModSI();
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@ -673,6 +675,7 @@ public:
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case ImmTyNegLo: OS << "NegLo"; break;
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case ImmTyNegHi: OS << "NegHi"; break;
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case ImmTySwizzle: OS << "Swizzle"; break;
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case ImmTyHigh: OS << "High"; break;
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}
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}
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@ -1064,6 +1067,8 @@ public:
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void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
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void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);
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void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
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void cvtMIMG(MCInst &Inst, const OperandVector &Operands,
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bool IsAtomic = false);
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void cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands);
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@ -4020,6 +4025,7 @@ static const OptionalOperand AMDGPUOptionalOperandTable[] = {
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{"glc", AMDGPUOperand::ImmTyGLC, true, nullptr},
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{"slc", AMDGPUOperand::ImmTySLC, true, nullptr},
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{"tfe", AMDGPUOperand::ImmTyTFE, true, nullptr},
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{"high", AMDGPUOperand::ImmTyHigh, true, nullptr},
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{"clamp", AMDGPUOperand::ImmTyClampSI, true, nullptr},
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{"omod", AMDGPUOperand::ImmTyOModSI, false, ConvertOmodMul},
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{"unorm", AMDGPUOperand::ImmTyUNorm, true, nullptr},
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@ -4122,6 +4128,45 @@ static bool isRegOrImmWithInputMods(const MCInstrDesc &Desc, unsigned OpNum) {
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&& Desc.getOperandConstraint(OpNum + 1, MCOI::OperandConstraint::TIED_TO) == -1;
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}
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void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands) {
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OptionalImmIndexMap OptionalIdx;
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unsigned Opc = Inst.getOpcode();
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unsigned I = 1;
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const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
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for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
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((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
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}
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for (unsigned E = Operands.size(); I != E; ++I) {
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AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
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if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
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Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
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} else if (Op.isInterpSlot() ||
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Op.isInterpAttr() ||
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Op.isAttrChan()) {
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Inst.addOperand(MCOperand::createImm(Op.Imm.Val));
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} else if (Op.isImmModifier()) {
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OptionalIdx[Op.getImmTy()] = I;
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} else {
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llvm_unreachable("unhandled operand type");
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}
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}
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if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::high) != -1) {
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyHigh);
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}
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if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) {
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
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}
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if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) {
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
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}
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}
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void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,
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OptionalImmIndexMap &OptionalIdx) {
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unsigned Opc = Inst.getOpcode();
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@ -981,6 +981,13 @@ void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
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printIfSet(MI, OpNo, O, "_SAT");
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}
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void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).getImm())
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O << " high";
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}
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void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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@ -170,6 +170,8 @@ private:
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char Asm);
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void printAbs(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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raw_ostream &O);
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void printHigh(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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raw_ostream &O);
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void printClamp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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raw_ostream &O);
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void printClampSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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@ -556,6 +556,7 @@ def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>;
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def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>;
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def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>;
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def highmod : NamedOperandBit<"High", NamedMatchClass<"High">>;
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def GLC : NamedOperandBit<"GLC", NamedMatchClass<"GLC">>;
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def slc : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>;
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@ -1511,6 +1512,7 @@ class VOPProfile <list<ValueType> _ArgVT> {
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field bit HasClamp = HasModifiers;
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field bit HasSDWAClamp = EmitDst;
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field bit HasFPClamp = BitAnd<isFloatType<DstVT>.ret, HasClamp>.ret;
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field bit HasHigh = 0;
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field bit IsPacked = isPackedType<Src0VT>.ret;
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field bit HasOpSel = IsPacked;
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@ -174,6 +174,68 @@ def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> {
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let Asm64 = " $vdst, $sdst, $src0, $src1, $src2";
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}
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//===----------------------------------------------------------------------===//
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// VOP3 INTERP
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//===----------------------------------------------------------------------===//
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class VOP3Interp<string OpName, VOPProfile P> : VOP3_Pseudo<OpName, P> {
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let AsmMatchConverter = "cvtVOP3Interp";
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}
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def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> {
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let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
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Attr:$attr, AttrChan:$attrchan,
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clampmod:$clamp, omod:$omod);
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let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod";
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}
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def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> {
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let Ins64 = (ins InterpSlot:$src0,
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Attr:$attr, AttrChan:$attrchan,
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clampmod:$clamp, omod:$omod);
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let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
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let HasClamp = 1;
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}
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class getInterp16Asm <bit HasSrc2, bit HasOMod> {
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string src2 = !if(HasSrc2, ", $src2_modifiers", "");
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string omod = !if(HasOMod, "$omod", "");
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string ret =
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" $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod;
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}
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class getInterp16Ins <bit HasSrc2, bit HasOMod,
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Operand Src0Mod, Operand Src2Mod> {
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dag ret = !if(HasSrc2,
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!if(HasOMod,
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(ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
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Attr:$attr, AttrChan:$attrchan,
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Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
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highmod:$high, clampmod:$clamp, omod:$omod),
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(ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
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Attr:$attr, AttrChan:$attrchan,
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Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
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highmod:$high, clampmod:$clamp)
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),
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(ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
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Attr:$attr, AttrChan:$attrchan,
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highmod:$high, clampmod:$clamp, omod:$omod)
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);
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}
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class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
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let HasOMod = !if(!eq(DstVT.Value, f16.Value), 0, 1);
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let HasHigh = 1;
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let Outs64 = (outs VGPR_32:$vdst);
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let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret;
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let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret;
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}
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//===----------------------------------------------------------------------===//
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// VOP3 Instructions
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//===----------------------------------------------------------------------===//
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@ -315,9 +377,11 @@ def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F1
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let isCommutable = 1 in {
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def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>;
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def V_INTERP_P1LL_F16 : VOP3Inst <"v_interp_p1ll_f16", VOP3_Profile<VOP_F32_F32_F16>>;
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def V_INTERP_P1LV_F16 : VOP3Inst <"v_interp_p1lv_f16", VOP3_Profile<VOP_F32_F32_F16_F16>>;
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def V_INTERP_P2_F16 : VOP3Inst <"v_interp_p2_f16", VOP3_Profile<VOP_F16_F32_F16_F32>>;
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def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>>;
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def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>;
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def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>>;
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def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
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def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
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@ -327,6 +391,10 @@ def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
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} // End SubtargetPredicate = Has16BitInsts
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let SubtargetPredicate = isVI in {
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def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>;
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def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>;
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def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>;
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def V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
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} // End SubtargetPredicate = isVI
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@ -512,6 +580,11 @@ multiclass VOP3OpSel_Real_gfx9<bits<10> op> {
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VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
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}
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multiclass VOP3Interp_Real_vi<bits<10> op> {
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def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
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VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
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}
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} // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
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defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>;
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@ -567,9 +640,13 @@ defm V_PERM_B32 : VOP3_Real_vi <0x1ed>;
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defm V_FMA_F16 : VOP3_Real_vi <0x1ee>;
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defm V_DIV_FIXUP_F16 : VOP3_Real_vi <0x1ef>;
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defm V_INTERP_P1LL_F16 : VOP3_Real_vi <0x274>;
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defm V_INTERP_P1LV_F16 : VOP3_Real_vi <0x275>;
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defm V_INTERP_P2_F16 : VOP3_Real_vi <0x276>;
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defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_vi <0x270>;
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defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_vi <0x271>;
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defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>;
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defm V_INTERP_P1LL_F16 : VOP3Interp_Real_vi <0x274>;
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defm V_INTERP_P1LV_F16 : VOP3Interp_Real_vi <0x275>;
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defm V_INTERP_P2_F16 : VOP3Interp_Real_vi <0x276>;
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defm V_ADD_F64 : VOP3_Real_vi <0x280>;
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defm V_MUL_F64 : VOP3_Real_vi <0x281>;
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defm V_MIN_F64 : VOP3_Real_vi <0x282>;
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@ -204,6 +204,25 @@ class VOP3OpSel_gfx9 <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> {
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let Inst{14} = !if(P.HasDst, src0_modifiers{3}, 0);
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}
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// NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa
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class VOP3Interp_vi <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> {
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bits<2> attrchan;
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bits<6> attr;
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bits<1> high;
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let Inst{8} = 0; // No modifiers for src0
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let Inst{61} = 0;
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let Inst{9} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0);
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let Inst{62} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0);
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let Inst{37-32} = attr;
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let Inst{39-38} = attrchan;
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let Inst{40} = !if(P.HasHigh, high, 0);
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let Inst{49-41} = src0;
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}
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class VOP3be <VOPProfile P> : Enc64 {
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bits<8> vdst;
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bits<2> src0_modifiers;
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@ -44,4 +44,36 @@ v_cmp_le_f64_e64 vcc, v0, v1 mul:4
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// GCN: error: invalid operand for instruction
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v_cvt_u32_f32_e64 v0, v1 div:2
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// GCN: error: invalid operand for instruction
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// GCN: error: invalid operand for instruction
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//
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// v_interp*
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//
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v_interp_mov_f32_e64 v5, p10, attr0.x high
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// GCN: error: invalid operand for instruction
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v_interp_mov_f32_e64 v5, p10, attr0.x v0
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// GCN: error: invalid operand for instruction
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v_interp_p1_f32_e64 v5, v2, attr0.x high
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// GCN: error: invalid operand for instruction
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v_interp_p1_f32_e64 v5, v2, attr0.x v0
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// GCN: error: invalid operand for instruction
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v_interp_p2_f32_e64 v255, v2, attr0.x high
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// GCN: error: invalid operand for instruction
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v_interp_p2_f32_e64 v255, v2, attr0.x v0
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// GCN: error: invalid operand for instruction
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v_interp_p1ll_f16 v5, p0, attr31.x
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// GCN: error: invalid operand for instruction
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v_interp_p1ll_f16 v5, v2, attr31.x v0
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// GCN: error: invalid operand for instruction
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v_interp_p2_f16 v5, v2, attr1.x, v3 mul:2
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// GFX67: error: not a valid operand
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// GFX89: error: invalid operand for instruction
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@ -435,3 +435,208 @@ v_mul_f64 v[0:1], |0|, |0|
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v_cubeid_f32 v0, |-1|, |-1.0|, |1.0|
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// SICI: v_cubeid_f32 v0, |-1|, |-1.0|, |1.0| ; encoding: [0x00,0x07,0x88,0xd2,0xc1,0xe6,0xc9,0x03]
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// VI: v_cubeid_f32 v0, |-1|, |-1.0|, |1.0| ; encoding: [0x00,0x07,0xc4,0xd1,0xc1,0xe6,0xc9,0x03]
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//
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// v_interp*
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//
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v_interp_mov_f32_e64 v5, p10, attr0.x
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// NOSICI: error: instruction not supported on this GPU
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// VI: v_interp_mov_f32_e64 v5, p10, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
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v_interp_mov_f32_e64 v5, p10, attr32.x
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// NOSICI: error: instruction not supported on this GPU
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// VI: v_interp_mov_f32_e64 v5, p10, attr32.x ; encoding: [0x05,0x00,0x72,0xd2,0x20,0x00,0x00,0x00]
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v_interp_mov_f32_e64 v5, p20, attr0.x
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// NOSICI: error: instruction not supported on this GPU
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// VI: v_interp_mov_f32_e64 v5, p20, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x02,0x00,0x00]
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v_interp_mov_f32_e64 v5, p10, attr0.w
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// NOSICI: error: instruction not supported on this GPU
|
||||
// VI: v_interp_mov_f32_e64 v5, p10, attr0.w ; encoding: [0x05,0x00,0x72,0xd2,0xc0,0x00,0x00,0x00]
|
||||
|
||||
v_interp_mov_f32_e64 v5, p10, attr0.x clamp
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_mov_f32_e64 v5, p10, attr0.x clamp ; encoding: [0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr0.x clamp
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_mov_f32_e64 v5, p10, attr0.x clamp ; encoding: [0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00]
|
||||
|
||||
v_interp_mov_f32_e64 v5, p10, attr0.x mul:2
|
||||
// NOSICI: error: not a valid operand
|
||||
// VI: v_interp_mov_f32_e64 v5, p10, attr0.x mul:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x08]
|
||||
|
||||
v_interp_mov_f32_e64 v5, p10, attr0.x mul:4
|
||||
// NOSICI: error: not a valid operand
|
||||
// VI: v_interp_mov_f32_e64 v5, p10, attr0.x mul:4 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x10]
|
||||
|
||||
v_interp_mov_f32_e64 v5, p10, attr0.x div:2
|
||||
// NOSICI: error: not a valid operand
|
||||
// VI: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr0.x div:2
|
||||
// NOSICI: error: not a valid operand
|
||||
// VI: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18]
|
||||
|
||||
|
||||
v_interp_p1_f32_e64 v5, v2, attr0.x
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// VI: v_interp_p1_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
|
||||
|
||||
v_interp_p1_f32_e64 v5, v2, attr0.y
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// VI: v_interp_p1_f32_e64 v5, v2, attr0.y ; encoding: [0x05,0x00,0x70,0xd2,0x40,0x04,0x02,0x00]
|
||||
|
||||
v_interp_p1_f32_e64 v5, -v2, attr0.x
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p1_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x40]
|
||||
|
||||
v_interp_p1_f32_e64 v5, |v2|, attr0.x
|
||||
// NOSICI: error: not a valid operand
|
||||
// VI: v_interp_p1_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x70,0xd2,0x00,0x04,0x02,0x00]
|
||||
|
||||
v_interp_p1_f32_e64 v5, v2, attr0.x clamp
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p1_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00]
|
||||
|
||||
v_interp_p1_f32 v5, v2, attr0.x clamp
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p1_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00]
|
||||
|
||||
v_interp_p1_f32_e64 v5, v2, attr0.x mul:2
|
||||
// NOSICI: error: not a valid operand
|
||||
// VI: v_interp_p1_f32_e64 v5, v2, attr0.x mul:2 ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x08]
|
||||
|
||||
|
||||
v_interp_p2_f32_e64 v255, v2, attr0.x
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// VI: v_interp_p2_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x71,0xd2,0x00,0x04,0x02,0x00]
|
||||
|
||||
v_interp_p2_f32_e64 v5, v2, attr31.x
|
||||
// NOSICI: error: instruction not supported on this GPU
|
||||
// VI: v_interp_p2_f32_e64 v5, v2, attr31.x ; encoding: [0x05,0x00,0x71,0xd2,0x1f,0x04,0x02,0x00]
|
||||
|
||||
v_interp_p2_f32_e64 v5, -v2, attr0.x
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p2_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x40]
|
||||
|
||||
v_interp_p2_f32_e64 v5, |v2|, attr0.x
|
||||
// NOSICI: error: not a valid operand
|
||||
// VI: v_interp_p2_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x71,0xd2,0x00,0x04,0x02,0x00]
|
||||
|
||||
v_interp_p2_f32_e64 v5, v2, attr0.x clamp
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p2_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x71,0xd2,0x00,0x04,0x02,0x00]
|
||||
|
||||
v_interp_p2_f32_e64 v5, v2, attr0.x div:2
|
||||
// NOSICI: error: not a valid operand
|
||||
// VI: v_interp_p2_f32_e64 v5, v2, attr0.x div:2 ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x18]
|
||||
|
||||
|
||||
v_interp_p1ll_f16 v5, v2, attr31.x
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p1ll_f16 v5, v2, attr31.x ; encoding: [0x05,0x00,0x74,0xd2,0x1f,0x04,0x02,0x00]
|
||||
|
||||
v_interp_p1ll_f16 v5, v2, attr0.w
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p1ll_f16 v5, v2, attr0.w ; encoding: [0x05,0x00,0x74,0xd2,0xc0,0x04,0x02,0x00]
|
||||
|
||||
v_interp_p1ll_f16 v5, -v2, attr0.x
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p1ll_f16 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x40]
|
||||
|
||||
v_interp_p1ll_f16 v5, |v2|, attr0.x
|
||||
// NOSICI: error: not a valid operand
|
||||
// VI: v_interp_p1ll_f16 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x74,0xd2,0x00,0x04,0x02,0x00]
|
||||
|
||||
v_interp_p1ll_f16 v5, v2, attr0.x high
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p1ll_f16 v5, v2, attr0.x high ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x05,0x02,0x00]
|
||||
|
||||
v_interp_p1ll_f16 v5, v2, attr0.x clamp
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p1ll_f16 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x74,0xd2,0x00,0x04,0x02,0x00]
|
||||
|
||||
v_interp_p1ll_f16 v5, v2, attr0.x mul:4
|
||||
// NOSICI: error: not a valid operand
|
||||
// VI: v_interp_p1ll_f16 v5, v2, attr0.x mul:4 ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x10]
|
||||
|
||||
|
||||
v_interp_p1lv_f16 v5, v2, attr1.x, v3
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p1lv_f16 v5, v2, attr1.x, v3 ; encoding: [0x05,0x00,0x75,0xd2,0x01,0x04,0x0e,0x04]
|
||||
|
||||
v_interp_p1lv_f16 v5, v2, attr0.z, v3
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p1lv_f16 v5, v2, attr0.z, v3 ; encoding: [0x05,0x00,0x75,0xd2,0x80,0x04,0x0e,0x04]
|
||||
|
||||
v_interp_p1lv_f16 v5, -v2, attr0.x, v3
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p1lv_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x44]
|
||||
|
||||
v_interp_p1lv_f16 v5, v2, attr0.x, -v3
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p1lv_f16 v5, v2, attr0.x, -v3 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x84]
|
||||
|
||||
v_interp_p1lv_f16 v5, |v2|, attr0.x, v3
|
||||
// NOSICI: error: not a valid operand
|
||||
// VI: v_interp_p1lv_f16 v5, |v2|, attr0.x, v3 ; encoding: [0x05,0x02,0x75,0xd2,0x00,0x04,0x0e,0x04]
|
||||
|
||||
v_interp_p1lv_f16 v5, v2, attr0.x, |v3|
|
||||
// NOSICI: error: not a valid operand
|
||||
// VI: v_interp_p1lv_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x75,0xd2,0x00,0x04,0x0e,0x04]
|
||||
|
||||
v_interp_p1lv_f16 v5, v2, attr0.x, v3 high
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x05,0x0e,0x04]
|
||||
|
||||
v_interp_p1lv_f16 v5, v2, attr0.x, v3 clamp
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x75,0xd2,0x00,0x04,0x0e,0x04]
|
||||
|
||||
v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:2
|
||||
// NOSICI: error: not a valid operand
|
||||
// VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:2 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x0c]
|
||||
|
||||
v_interp_p1lv_f16 v5, v2, attr0.x, v3 div:2
|
||||
// NOSICI: error: not a valid operand
|
||||
// VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 div:2 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x1c]
|
||||
|
||||
|
||||
v_interp_p2_f16 v5, v2, attr1.x, v3
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p2_f16 v5, v2, attr1.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x01,0x04,0x0e,0x04]
|
||||
|
||||
v_interp_p2_f16 v5, v2, attr32.x, v3
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p2_f16 v5, v2, attr32.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x20,0x04,0x0e,0x04]
|
||||
|
||||
v_interp_p2_f16 v5, v2, attr0.w, v3
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p2_f16 v5, v2, attr0.w, v3 ; encoding: [0x05,0x00,0x76,0xd2,0xc0,0x04,0x0e,0x04]
|
||||
|
||||
v_interp_p2_f16 v5, -v2, attr0.x, v3
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p2_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44]
|
||||
|
||||
v_interp_p2_f16 v5, v2, attr0.x, -v3
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p2_f16 v5, v2, attr0.x, -v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x84]
|
||||
|
||||
v_interp_p2_f16 v5, |v2|, attr0.x, v3
|
||||
// NOSICI: error: not a valid operand
|
||||
// VI: v_interp_p2_f16 v5, |v2|, attr0.x, v3 ; encoding: [0x05,0x02,0x76,0xd2,0x00,0x04,0x0e,0x04]
|
||||
|
||||
v_interp_p2_f16 v5, v2, attr0.x, |v3|
|
||||
// NOSICI: error: not a valid operand
|
||||
// VI: v_interp_p2_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04]
|
||||
|
||||
v_interp_p2_f16 v5, v2, attr0.x, v3 high
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p2_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
|
||||
|
||||
v_interp_p2_f16 v5, v2, attr0.x, v3 clamp
|
||||
// NOSICI: error: invalid operand for instruction
|
||||
// VI: v_interp_p2_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
|
||||
|
||||
@ -239,3 +239,144 @@
|
||||
|
||||
# VI: v_ceil_f32_e64 v0, neg(-1.0) ; encoding: [0x00,0x00,0x5d,0xd1,0xf3,0x00,0x00,0x20]
|
||||
0x00,0x00,0x5d,0xd1,0xf3,0x00,0x00,0x20
|
||||
|
||||
# VI: v_interp_mov_f32_e64 v5, p10, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
|
||||
0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00
|
||||
|
||||
# VI: v_interp_mov_f32_e64 v5, p10, attr32.x ; encoding: [0x05,0x00,0x72,0xd2,0x20,0x00,0x00,0x00]
|
||||
0x05,0x00,0x72,0xd2,0x20,0x00,0x00,0x00
|
||||
|
||||
# VI: v_interp_mov_f32_e64 v5, p20, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x02,0x00,0x00]
|
||||
0x05,0x00,0x72,0xd2,0x00,0x02,0x00,0x00
|
||||
|
||||
# VI: v_interp_mov_f32_e64 v5, p10, attr0.w ; encoding: [0x05,0x00,0x72,0xd2,0xc0,0x00,0x00,0x00]
|
||||
0x05,0x00,0x72,0xd2,0xc0,0x00,0x00,0x00
|
||||
|
||||
# VI: v_interp_mov_f32_e64 v5, p10, attr0.x clamp ; encoding: [0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00]
|
||||
0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00
|
||||
|
||||
# VI: v_interp_mov_f32_e64 v5, p10, attr0.x mul:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x08]
|
||||
0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x08
|
||||
|
||||
# VI: v_interp_mov_f32_e64 v5, p10, attr0.x mul:4 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x10]
|
||||
0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x10
|
||||
|
||||
# VI: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18]
|
||||
0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18
|
||||
|
||||
# VI: v_interp_p1_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
|
||||
0xff,0x00,0x70,0xd2,0x00,0x04,0x02,0x00
|
||||
|
||||
# VI: v_interp_p1_f32_e64 v5, v2, attr1.x ; encoding: [0x05,0x00,0x70,0xd2,0x01,0x04,0x02,0x00]
|
||||
0x05,0x00,0x70,0xd2,0x01,0x04,0x02,0x00
|
||||
|
||||
# VI: v_interp_p1_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x40]
|
||||
0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x40
|
||||
|
||||
# VI: v_interp_p1_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x70,0xd2,0x00,0x04,0x02,0x00]
|
||||
0x05,0x02,0x70,0xd2,0x00,0x04,0x02,0x00
|
||||
|
||||
# VI: v_interp_p1_f32_e64 v5, v2, attr0.z ; encoding: [0x05,0x00,0x70,0xd2,0x80,0x04,0x02,0x00]
|
||||
0x05,0x00,0x70,0xd2,0x80,0x04,0x02,0x00
|
||||
|
||||
# VI: v_interp_p1_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00]
|
||||
0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00
|
||||
|
||||
# VI: v_interp_p1_f32_e64 v5, v2, attr0.x mul:2 ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x08]
|
||||
0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x08
|
||||
|
||||
# VI: v_interp_p2_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x00]
|
||||
0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x00
|
||||
|
||||
# VI: v_interp_p2_f32_e64 v5, v2, attr31.x ; encoding: [0x05,0x00,0x71,0xd2,0x1f,0x04,0x02,0x00]
|
||||
0x05,0x00,0x71,0xd2,0x1f,0x04,0x02,0x00
|
||||
|
||||
# VI: v_interp_p2_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x40]
|
||||
0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x40
|
||||
|
||||
# VI: v_interp_p2_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x71,0xd2,0x00,0x04,0x02,0x00]
|
||||
0x05,0x02,0x71,0xd2,0x00,0x04,0x02,0x00
|
||||
|
||||
# VI: v_interp_p2_f32_e64 v5, v2, attr0.y ; encoding: [0x05,0x00,0x71,0xd2,0x40,0x04,0x02,0x00]
|
||||
0x05,0x00,0x71,0xd2,0x40,0x04,0x02,0x00
|
||||
|
||||
# VI: v_interp_p2_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x71,0xd2,0x00,0x04,0x02,0x00]
|
||||
0x05,0x80,0x71,0xd2,0x00,0x04,0x02,0x00
|
||||
|
||||
# VI: v_interp_p2_f32_e64 v5, v2, attr0.x mul:4 ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x10]
|
||||
0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x10
|
||||
|
||||
# VI: v_interp_p1ll_f16 v5, v2, attr0.x ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x00]
|
||||
0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x00
|
||||
|
||||
# VI: v_interp_p1ll_f16 v5, v2, attr1.x ; encoding: [0x05,0x00,0x74,0xd2,0x01,0x04,0x02,0x00]
|
||||
0x05,0x00,0x74,0xd2,0x01,0x04,0x02,0x00
|
||||
|
||||
# VI: v_interp_p1ll_f16 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x40]
|
||||
0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x40
|
||||
|
||||
# VI: v_interp_p1ll_f16 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x74,0xd2,0x00,0x04,0x02,0x00]
|
||||
0x05,0x02,0x74,0xd2,0x00,0x04,0x02,0x00
|
||||
|
||||
# VI: v_interp_p1ll_f16 v5, v2, attr0.y ; encoding: [0x05,0x00,0x74,0xd2,0x40,0x04,0x02,0x00]
|
||||
0x05,0x00,0x74,0xd2,0x40,0x04,0x02,0x00
|
||||
|
||||
# VI: v_interp_p1ll_f16 v5, v2, attr0.x high ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x05,0x02,0x00]
|
||||
0x05,0x00,0x74,0xd2,0x00,0x05,0x02,0x00
|
||||
|
||||
# VI: v_interp_p1ll_f16 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x74,0xd2,0x00,0x04,0x02,0x00]
|
||||
0x05,0x80,0x74,0xd2,0x00,0x04,0x02,0x00
|
||||
|
||||
# VI: v_interp_p1ll_f16 v5, v2, attr0.x div:2 ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x18]
|
||||
0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x18
|
||||
|
||||
# VI: v_interp_p1lv_f16 v255, v2, attr0.x, v3 ; encoding: [0xff,0x00,0x75,0xd2,0x00,0x04,0x0e,0x04]
|
||||
0xff,0x00,0x75,0xd2,0x00,0x04,0x0e,0x04
|
||||
|
||||
# VI: v_interp_p1lv_f16 v5, v2, attr32.x, v3 ; encoding: [0x05,0x00,0x75,0xd2,0x20,0x04,0x0e,0x04]
|
||||
0x05,0x00,0x75,0xd2,0x20,0x04,0x0e,0x04
|
||||
|
||||
# VI: v_interp_p1lv_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x44]
|
||||
0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x44
|
||||
|
||||
# VI: v_interp_p1lv_f16 v5, v2, attr0.x, -v3 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x84]
|
||||
0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x84
|
||||
|
||||
# VI: v_interp_p1lv_f16 v5, |v2|, attr0.x, v3 ; encoding: [0x05,0x02,0x75,0xd2,0x00,0x04,0x0e,0x04]
|
||||
0x05,0x02,0x75,0xd2,0x00,0x04,0x0e,0x04
|
||||
|
||||
# VI: v_interp_p1lv_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x75,0xd2,0x00,0x04,0x0e,0x04]
|
||||
0x05,0x04,0x75,0xd2,0x00,0x04,0x0e,0x04
|
||||
|
||||
# VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x05,0x0e,0x04]
|
||||
0x05,0x00,0x75,0xd2,0x00,0x05,0x0e,0x04
|
||||
|
||||
# VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x75,0xd2,0x00,0x04,0x0e,0x04]
|
||||
0x05,0x80,0x75,0xd2,0x00,0x04,0x0e,0x04
|
||||
|
||||
# VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:4 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x14]
|
||||
0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x14
|
||||
|
||||
# VI: v_interp_p2_f16 v5, v2, attr0.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x04]
|
||||
0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x04
|
||||
|
||||
# VI: v_interp_p2_f16 v5, v2, attr1.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x01,0x04,0x0e,0x04]
|
||||
0x05,0x00,0x76,0xd2,0x01,0x04,0x0e,0x04
|
||||
|
||||
# VI: v_interp_p2_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44]
|
||||
0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44
|
||||
|
||||
# VI: v_interp_p2_f16 v5, v2, attr0.x, -v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x84]
|
||||
0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x84
|
||||
|
||||
# VI: v_interp_p2_f16 v5, |v2|, attr0.x, v3 ; encoding: [0x05,0x02,0x76,0xd2,0x00,0x04,0x0e,0x04]
|
||||
0x05,0x02,0x76,0xd2,0x00,0x04,0x0e,0x04
|
||||
|
||||
# VI: v_interp_p2_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04]
|
||||
0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04
|
||||
|
||||
# VI: v_interp_p2_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
|
||||
0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04
|
||||
|
||||
# VI: v_interp_p2_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
|
||||
0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user