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Delete some dead code.

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Found by gcc 6.

llvm-svn: 273303
This commit is contained in:
Rafael Espindola 2016-06-21 19:48:12 +00:00
parent c49d776c67
commit cd2c189f82
10 changed files with 0 additions and 104 deletions
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5
lib/CodeGen/MachineVerifier.cpp
View File

@ -219,7 +219,6 @@ namespace {
void report_context(const VNInfo &VNI) const;
void report_context(SlotIndex Pos) const;
void report_context_liverange(const LiveRange &LR) const;
void report_context_regunit(unsigned RegUnit) const;
void report_context_lanemask(LaneBitmask LaneMask) const;
void report_context_vreg(unsigned VReg) const;
void report_context_vreg_regunit(unsigned VRegOrRegUnit) const;
@ -495,10 +494,6 @@ void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
errs() << "- liverange: " << LR << '\n';
}
void MachineVerifier::report_context_regunit(unsigned RegUnit) const {
errs() << "- regunit: " << PrintRegUnit(RegUnit, TRI) << '\n';
}
void MachineVerifier::report_context_vreg(unsigned VReg) const {
errs() << "- v. register: " << PrintReg(VReg, TRI) << '\n';
}

8
lib/MC/ELFObjectWriter.cpp
View File

@ -70,7 +70,6 @@ public:
};
class ELFObjectWriter : public MCObjectWriter {
static bool isFixupKindPCRel(const MCAssembler &Asm, unsigned Kind);
static uint64_t SymbolValue(const MCSymbol &Sym, const MCAsmLayout &Layout);
static bool isInSymtab(const MCAsmLayout &Layout, const MCSymbolELF &Symbol,
bool Used, bool Renamed);
@ -298,13 +297,6 @@ void SymbolTableWriter::writeSymbol(uint32_t name, uint8_t info, uint64_t value,
++NumWritten;
}
bool ELFObjectWriter::isFixupKindPCRel(const MCAssembler &Asm, unsigned Kind) {
const MCFixupKindInfo &FKI =
Asm.getBackend().getFixupKindInfo((MCFixupKind) Kind);
return FKI.Flags & MCFixupKindInfo::FKF_IsPCRel;
}
ELFObjectWriter::~ELFObjectWriter()
{}

3
lib/MC/WinCOFFObjectWriter.cpp
View File

@ -109,7 +109,6 @@ public:
relocations Relocations;
COFFSection(StringRef name);
static size_t size();
};
class WinCOFFObjectWriter : public MCObjectWriter {
@ -224,8 +223,6 @@ COFFSection::COFFSection(StringRef name)
memset(&Header, 0, sizeof(Header));
}
size_t COFFSection::size() { return COFF::SectionSize; }
//------------------------------------------------------------------------------
// WinCOFFObjectWriter class implementation

5
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
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@ -85,7 +85,6 @@ private:
static bool isFlatStore(const MemSDNode *N);
static bool isPrivateStore(const StoreSDNode *N);
static bool isLocalStore(const StoreSDNode *N);
static bool isRegionStore(const StoreSDNode *N);
bool isCPLoad(const LoadSDNode *N) const;
bool isConstantLoad(const MemSDNode *N, int cbID) const;
@ -599,10 +598,6 @@ bool AMDGPUDAGToDAGISel::isFlatStore(const MemSDNode *N) {
return checkType(N->getMemOperand()->getValue(), AMDGPUAS::FLAT_ADDRESS);
}
bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
}
bool AMDGPUDAGToDAGISel::isConstantLoad(const MemSDNode *N, int CbId) const {
if (!N->readMem())
return false;

5
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
View File

@ -694,7 +694,6 @@ public:
void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, false); }
void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, false); }
void cvtMubufAtomicReturn(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, true); }
AMDGPUOperand::Ptr defaultMubufOffset() const;
AMDGPUOperand::Ptr defaultGLC() const;
AMDGPUOperand::Ptr defaultSLC() const;
AMDGPUOperand::Ptr defaultTFE() const;
@ -2136,10 +2135,6 @@ bool AMDGPUOperand::isMubufOffset() const {
return isImmTy(ImmTyOffset) && isUInt<12>(getImm());
}
AMDGPUOperand::Ptr AMDGPUAsmParser::defaultMubufOffset() const {
return AMDGPUOperand::CreateImm(0, SMLoc(), AMDGPUOperand::ImmTyOffset);
}
AMDGPUOperand::Ptr AMDGPUAsmParser::defaultGLC() const {
return AMDGPUOperand::CreateImm(0, SMLoc(), AMDGPUOperand::ImmTyGLC);
}

15
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
View File

@ -69,10 +69,6 @@ private:
MachineBasicBlock::iterator findMatchingDSInst(MachineBasicBlock::iterator I,
unsigned EltSize);
void updateRegDefsUses(unsigned SrcReg,
unsigned DstReg,
unsigned SubIdx);
MachineBasicBlock::iterator mergeRead2Pair(
MachineBasicBlock::iterator I,
MachineBasicBlock::iterator Paired,
@ -193,17 +189,6 @@ SILoadStoreOptimizer::findMatchingDSInst(MachineBasicBlock::iterator I,
return E;
}
void SILoadStoreOptimizer::updateRegDefsUses(unsigned SrcReg,
unsigned DstReg,
unsigned SubIdx) {
for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg),
E = MRI->reg_end(); I != E; ) {
MachineOperand &O = *I;
++I;
O.substVirtReg(DstReg, SubIdx, *TRI);
}
}
MachineBasicBlock::iterator SILoadStoreOptimizer::mergeRead2Pair(
MachineBasicBlock::iterator I,
MachineBasicBlock::iterator Paired,

25
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -246,9 +246,6 @@ class MipsAsmParser : public MCTargetAsmParser {
bool expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
void createCpRestoreMemOp(bool IsLoad, int StackOffset, SMLoc IDLoc,
MCStreamer &Out, const MCSubtargetInfo *STI);
bool reportParseError(Twine ErrorMsg);
bool reportParseError(SMLoc Loc, Twine ErrorMsg);
@ -323,8 +320,6 @@ class MipsAsmParser : public MCTargetAsmParser {
unsigned getReg(int RC, int RegNo);
unsigned getGPR(int RegNo);
/// Returns the internal register number for the current AT. Also checks if
/// the current AT is unavailable (set to $0) and gives an error if it is.
/// This should be used in pseudo-instruction expansions which need AT.
@ -3699,21 +3694,6 @@ bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
return false;
}
void MipsAsmParser::createCpRestoreMemOp(bool IsLoad, int StackOffset,
SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
if (IsLoad) {
TOut.emitLoadWithImmOffset(Mips::LW, Mips::GP, Mips::SP, StackOffset,
Mips::GP, IDLoc, STI);
return;
}
TOut.emitStoreWithImmOffset(Mips::SW, Mips::GP, Mips::SP, StackOffset,
[&]() { return getATReg(IDLoc); }, IDLoc, STI);
}
unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
switch (Inst.getOpcode()) {
// As described by the Mips32r2 spec, the registers Rd and Rs for
@ -4142,11 +4122,6 @@ unsigned MipsAsmParser::getReg(int RC, int RegNo) {
return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
}
unsigned MipsAsmParser::getGPR(int RegNo) {
return getReg(isGP64bit() ? Mips::GPR64RegClassID : Mips::GPR32RegClassID,
RegNo);
}
int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
if (RegNum >
getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs() - 1)

14
lib/Target/PowerPC/PPCFastISel.cpp
View File

@ -186,7 +186,6 @@ class PPCFastISel final : public FastISel {
unsigned &NumBytes,
bool IsVarArg);
bool finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes);
CCAssignFn *usePPC32CCs(unsigned Flag);
private:
#include "PPCGenFastISel.inc"
@ -197,19 +196,6 @@ class PPCFastISel final : public FastISel {
#include "PPCGenCallingConv.inc"
// Function whose sole purpose is to kill compiler warnings
// stemming from unused functions included from PPCGenCallingConv.inc.
CCAssignFn *PPCFastISel::usePPC32CCs(unsigned Flag) {
if (Flag == 1)
return CC_PPC32_SVR4;
else if (Flag == 2)
return CC_PPC32_SVR4_ByVal;
else if (Flag == 3)
return CC_PPC32_SVR4_VarArg;
else
return RetCC_PPC;
}
static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) {
switch (Pred) {
// These are not representable with any single compare.

8
lib/Transforms/Scalar/LoopInterchange.cpp
View File

@ -408,7 +408,6 @@ private:
bool adjustLoopLinks();
void adjustLoopPreheaders();
void adjustOuterLoopPreheader();
void adjustInnerLoopPreheader();
bool adjustLoopBranches();
void updateIncomingBlock(BasicBlock *CurrBlock, BasicBlock *OldPred,
BasicBlock *NewPred);
@ -1133,13 +1132,6 @@ void LoopInterchangeTransform::adjustOuterLoopPreheader() {
moveBBContents(OuterLoopPreHeader, InnerPreHeader->getTerminator());
}
void LoopInterchangeTransform::adjustInnerLoopPreheader() {
BasicBlock *InnerLoopPreHeader = InnerLoop->getLoopPreheader();
BasicBlock *OuterHeader = OuterLoop->getHeader();
moveBBContents(InnerLoopPreHeader, OuterHeader->getTerminator());
}
void LoopInterchangeTransform::updateIncomingBlock(BasicBlock *CurrBlock,
BasicBlock *OldPred,
BasicBlock *NewPred) {

16
tools/llvm-readobj/COFFDumper.cpp
View File

@ -113,10 +113,6 @@ private:
uint32_t RelocOffset, uint32_t Offset,
StringRef *RelocSym = nullptr);
void printRelocatedField(StringRef Label, const coff_section *Sec,
StringRef SectionContents, const ulittle32_t *Field,
StringRef *RelocSym = nullptr);
void printBinaryBlockWithRelocs(StringRef Label, const SectionRef &Sec,
StringRef SectionContents, StringRef Block);
@ -264,18 +260,6 @@ void COFFDumper::printRelocatedField(StringRef Label, const coff_section *Sec,
W.printHex(Label, RelocOffset);
}
void COFFDumper::printRelocatedField(StringRef Label, const coff_section *Sec,
StringRef SectionContents,
const ulittle32_t *Field,
StringRef *RelocSym) {
StringRef SymStorage;
StringRef &Symbol = RelocSym ? *RelocSym : SymStorage;
if (!resolveSymbolName(Sec, SectionContents, Field, Symbol))
W.printSymbolOffset(Label, Symbol, *Field);
else
W.printHex(Label, *Field);
}
void COFFDumper::printBinaryBlockWithRelocs(StringRef Label,
const SectionRef &Sec,
StringRef SectionContents,