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hwasan: Improve precision of checks using short granule tags.
A short granule is a granule of size between 1 and `TG-1` bytes. The size of a short granule is stored at the location in shadow memory where the granule's tag is normally stored, while the granule's actual tag is stored in the last byte of the granule. This means that in order to verify that a pointer tag matches a memory tag, HWASAN must check for two possibilities: * the pointer tag is equal to the memory tag in shadow memory, or * the shadow memory tag is actually a short granule size, the value being loaded is in bounds of the granule and the pointer tag is equal to the last byte of the granule. Pointer tags between 1 to `TG-1` are possible and are as likely as any other tag. This means that these tags in memory have two interpretations: the full tag interpretation (where the pointer tag is between 1 and `TG-1` and the last byte of the granule is ordinary data) and the short tag interpretation (where the pointer tag is stored in the granule). When HWASAN detects an error near a memory tag between 1 and `TG-1`, it will show both the memory tag and the last byte of the granule. Currently, it is up to the user to disambiguate the two possibilities. Because this functionality obsoletes the right aligned heap feature of the HWASAN memory allocator (and because we can no longer easily test it), the feature is removed. Also update the documentation to cover both short granule tags and outlined checks. Differential Revision: https://reviews.llvm.org/D63908 llvm-svn: 365551
This commit is contained in:
Peter Collingbourne
parent
b925e6ebac
commit
cdc1df0c0c
@ -304,17 +304,82 @@ void AArch64AsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
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.addReg(Reg)
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.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)),
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*STI);
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MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
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MCSymbol *HandlePartialSym = OutContext.createTempSymbol();
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::Bcc)
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.addImm(AArch64CC::NE)
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.addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
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.addExpr(MCSymbolRefExpr::create(HandlePartialSym, OutContext)),
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*STI);
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MCSymbol *ReturnSym = OutContext.createTempSymbol();
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OutStreamer->EmitLabel(ReturnSym);
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::RET).addReg(AArch64::LR), *STI);
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OutStreamer->EmitLabel(HandleMismatchSym);
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OutStreamer->EmitLabel(HandlePartialSym);
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OutStreamer->EmitInstruction(MCInstBuilder(AArch64::SUBSWri)
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.addReg(AArch64::WZR)
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.addReg(AArch64::W16)
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.addImm(15)
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.addImm(0),
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*STI);
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MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::Bcc)
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.addImm(AArch64CC::HI)
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.addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
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*STI);
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::ANDXri)
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.addReg(AArch64::X17)
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.addReg(Reg)
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.addImm(AArch64_AM::encodeLogicalImmediate(0xf, 64)),
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*STI);
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size_t Size = 1 << (AccessInfo & 0xf);
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if (Size != 1)
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OutStreamer->EmitInstruction(MCInstBuilder(AArch64::ADDXri)
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.addReg(AArch64::X17)
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.addReg(AArch64::X17)
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.addImm(Size - 1)
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.addImm(0),
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*STI);
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OutStreamer->EmitInstruction(MCInstBuilder(AArch64::SUBSWrs)
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.addReg(AArch64::WZR)
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.addReg(AArch64::W16)
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.addReg(AArch64::W17)
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.addImm(0),
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*STI);
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::Bcc)
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.addImm(AArch64CC::LS)
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.addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
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*STI);
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::ORRXri)
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.addReg(AArch64::X16)
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.addReg(Reg)
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.addImm(AArch64_AM::encodeLogicalImmediate(0xf, 64)),
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*STI);
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OutStreamer->EmitInstruction(MCInstBuilder(AArch64::LDRBBui)
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.addReg(AArch64::W16)
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.addReg(AArch64::X16)
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.addImm(0),
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*STI);
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::SUBSXrs)
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.addReg(AArch64::XZR)
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.addReg(AArch64::X16)
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.addReg(Reg)
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.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)),
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*STI);
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::Bcc)
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.addImm(AArch64CC::EQ)
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.addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext)),
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*STI);
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OutStreamer->EmitLabel(HandleMismatchSym);
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OutStreamer->EmitInstruction(MCInstBuilder(AArch64::STPXpre)
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.addReg(AArch64::SP)
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.addReg(AArch64::X0)
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@ -198,7 +198,7 @@ public:
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Value **MaybeMask);
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bool isInterestingAlloca(const AllocaInst &AI);
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bool tagAlloca(IRBuilder<> &IRB, AllocaInst *AI, Value *Tag);
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bool tagAlloca(IRBuilder<> &IRB, AllocaInst *AI, Value *Tag, size_t Size);
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Value *tagPointer(IRBuilder<> &IRB, Type *Ty, Value *PtrLong, Value *Tag);
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Value *untagPointer(IRBuilder<> &IRB, Value *PtrLong);
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bool instrumentStack(
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@ -574,10 +574,35 @@ void HWAddressSanitizer::instrumentMemAccessInline(Value *Ptr, bool IsWrite,
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}
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Instruction *CheckTerm =
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SplitBlockAndInsertIfThen(TagMismatch, InsertBefore, !Recover,
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SplitBlockAndInsertIfThen(TagMismatch, InsertBefore, false,
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MDBuilder(*C).createBranchWeights(1, 100000));
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IRB.SetInsertPoint(CheckTerm);
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Value *OutOfShortGranuleTagRange =
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IRB.CreateICmpUGT(MemTag, ConstantInt::get(Int8Ty, 15));
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Instruction *CheckFailTerm =
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SplitBlockAndInsertIfThen(OutOfShortGranuleTagRange, CheckTerm, !Recover,
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MDBuilder(*C).createBranchWeights(1, 100000));
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IRB.SetInsertPoint(CheckTerm);
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Value *PtrLowBits = IRB.CreateTrunc(IRB.CreateAnd(PtrLong, 15), Int8Ty);
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PtrLowBits = IRB.CreateAdd(
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PtrLowBits, ConstantInt::get(Int8Ty, (1 << AccessSizeIndex) - 1));
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Value *PtrLowBitsOOB = IRB.CreateICmpUGE(PtrLowBits, MemTag);
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SplitBlockAndInsertIfThen(PtrLowBitsOOB, CheckTerm, false,
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MDBuilder(*C).createBranchWeights(1, 100000),
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nullptr, nullptr, CheckFailTerm->getParent());
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IRB.SetInsertPoint(CheckTerm);
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Value *InlineTagAddr = IRB.CreateOr(AddrLong, 15);
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InlineTagAddr = IRB.CreateIntToPtr(InlineTagAddr, Int8PtrTy);
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Value *InlineTag = IRB.CreateLoad(Int8Ty, InlineTagAddr);
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Value *InlineTagMismatch = IRB.CreateICmpNE(PtrTag, InlineTag);
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SplitBlockAndInsertIfThen(InlineTagMismatch, CheckTerm, false,
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MDBuilder(*C).createBranchWeights(1, 100000),
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nullptr, nullptr, CheckFailTerm->getParent());
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IRB.SetInsertPoint(CheckFailTerm);
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InlineAsm *Asm;
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switch (TargetTriple.getArch()) {
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case Triple::x86_64:
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@ -601,6 +626,8 @@ void HWAddressSanitizer::instrumentMemAccessInline(Value *Ptr, bool IsWrite,
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report_fatal_error("unsupported architecture");
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}
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IRB.CreateCall(Asm, PtrLong);
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if (Recover)
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cast<BranchInst>(CheckFailTerm)->setSuccessor(0, CheckTerm->getParent());
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}
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void HWAddressSanitizer::instrumentMemIntrinsic(MemIntrinsic *MI) {
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@ -677,15 +704,14 @@ static uint64_t getAllocaSizeInBytes(const AllocaInst &AI) {
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}
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bool HWAddressSanitizer::tagAlloca(IRBuilder<> &IRB, AllocaInst *AI,
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Value *Tag) {
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size_t Size = (getAllocaSizeInBytes(*AI) + Mapping.getAllocaAlignment() - 1) &
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~(Mapping.getAllocaAlignment() - 1);
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Value *Tag, size_t Size) {
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size_t AlignedSize = alignTo(Size, Mapping.getAllocaAlignment());
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Value *JustTag = IRB.CreateTrunc(Tag, IRB.getInt8Ty());
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if (ClInstrumentWithCalls) {
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IRB.CreateCall(HwasanTagMemoryFunc,
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{IRB.CreatePointerCast(AI, Int8PtrTy), JustTag,
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ConstantInt::get(IntptrTy, Size)});
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ConstantInt::get(IntptrTy, AlignedSize)});
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} else {
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size_t ShadowSize = Size >> Mapping.Scale;
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Value *ShadowPtr = memToShadow(IRB.CreatePointerCast(AI, IntptrTy), IRB);
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@ -695,7 +721,16 @@ bool HWAddressSanitizer::tagAlloca(IRBuilder<> &IRB, AllocaInst *AI,
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// FIXME: the interceptor is not as fast as real memset. Consider lowering
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// llvm.memset right here into either a sequence of stores, or a call to
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// hwasan_tag_memory.
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IRB.CreateMemSet(ShadowPtr, JustTag, ShadowSize, /*Align=*/1);
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if (ShadowSize)
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IRB.CreateMemSet(ShadowPtr, JustTag, ShadowSize, /*Align=*/1);
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if (Size != AlignedSize) {
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IRB.CreateStore(
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ConstantInt::get(Int8Ty, Size % Mapping.getAllocaAlignment()),
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IRB.CreateConstGEP1_32(Int8Ty, ShadowPtr, ShadowSize));
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IRB.CreateStore(JustTag, IRB.CreateConstGEP1_32(
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Int8Ty, IRB.CreateBitCast(AI, Int8PtrTy),
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AlignedSize - 1));
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}
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}
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return true;
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}
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@ -964,14 +999,15 @@ bool HWAddressSanitizer::instrumentStack(
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DDI->setArgOperand(2, MetadataAsValue::get(*C, NewExpr));
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}
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tagAlloca(IRB, AI, Tag);
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size_t Size = getAllocaSizeInBytes(*AI);
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tagAlloca(IRB, AI, Tag, Size);
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for (auto RI : RetVec) {
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IRB.SetInsertPoint(RI);
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// Re-tag alloca memory with the special UAR tag.
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Value *Tag = getUARTag(IRB, StackTag);
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tagAlloca(IRB, AI, Tag);
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tagAlloca(IRB, AI, Tag, alignTo(Size, Mapping.getAllocaAlignment()));
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}
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}
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@ -1012,11 +1048,6 @@ bool HWAddressSanitizer::sanitizeFunction(Function &F) {
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for (auto &Inst : BB) {
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if (ClInstrumentStack)
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if (AllocaInst *AI = dyn_cast<AllocaInst>(&Inst)) {
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// Realign all allocas. We don't want small uninteresting allocas to
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// hide in instrumented alloca's padding.
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if (AI->getAlignment() < Mapping.getAllocaAlignment())
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AI->setAlignment(Mapping.getAllocaAlignment());
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// Instrument some of them.
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if (isInterestingAlloca(*AI))
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AllocasToInstrument.push_back(AI);
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continue;
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@ -1068,6 +1099,45 @@ bool HWAddressSanitizer::sanitizeFunction(Function &F) {
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StackTag);
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}
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// Pad and align each of the allocas that we instrumented to stop small
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// uninteresting allocas from hiding in instrumented alloca's padding and so
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// that we have enough space to store real tags for short granules.
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DenseMap<AllocaInst *, AllocaInst *> AllocaToPaddedAllocaMap;
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for (AllocaInst *AI : AllocasToInstrument) {
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uint64_t Size = getAllocaSizeInBytes(*AI);
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uint64_t AlignedSize = alignTo(Size, Mapping.getAllocaAlignment());
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AI->setAlignment(std::max(AI->getAlignment(), 16u));
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if (Size != AlignedSize) {
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Type *TypeWithPadding = StructType::get(
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AI->getAllocatedType(), ArrayType::get(Int8Ty, AlignedSize - Size));
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auto *NewAI = new AllocaInst(
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TypeWithPadding, AI->getType()->getAddressSpace(), nullptr, "", AI);
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NewAI->takeName(AI);
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NewAI->setAlignment(AI->getAlignment());
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NewAI->setUsedWithInAlloca(AI->isUsedWithInAlloca());
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NewAI->setSwiftError(AI->isSwiftError());
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NewAI->copyMetadata(*AI);
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Value *Zero = ConstantInt::get(Int32Ty, 0);
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auto *GEP = GetElementPtrInst::Create(TypeWithPadding, NewAI,
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{Zero, Zero}, "", AI);
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AI->replaceAllUsesWith(GEP);
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AllocaToPaddedAllocaMap[AI] = NewAI;
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}
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}
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if (!AllocaToPaddedAllocaMap.empty()) {
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for (auto &BB : F)
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for (auto &Inst : BB)
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if (auto *DVI = dyn_cast<DbgVariableIntrinsic>(&Inst))
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if (auto *AI =
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dyn_cast_or_null<AllocaInst>(DVI->getVariableLocation()))
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if (auto *NewAI = AllocaToPaddedAllocaMap.lookup(AI))
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DVI->setArgOperand(
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0, MetadataAsValue::get(*C, LocalAsMetadata::get(NewAI)));
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for (auto &P : AllocaToPaddedAllocaMap)
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P.first->eraseFromParent();
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}
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// If we split the entry block, move any allocas that were originally in the
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// entry block back into the entry block so that they aren't treated as
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// dynamic allocas.
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@ -40,8 +40,20 @@ declare void @llvm.hwasan.check.memaccess(i8*, i8*, i32)
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; CHECK-NEXT: ldrb w16, [x9, x16]
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; CHECK-NEXT: cmp x16, x0, lsr #56
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; CHECK-NEXT: b.ne .Ltmp0
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; CHECK-NEXT: .Ltmp1:
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; CHECK-NEXT: ret
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; CHECK-NEXT: .Ltmp0:
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; CHECK-NEXT: cmp w16, #15
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; CHECK-NEXT: b.hi .Ltmp2
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; CHECK-NEXT: and x17, x0, #0xf
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; CHECK-NEXT: add x17, x17, #255
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; CHECK-NEXT: cmp w16, w17
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; CHECK-NEXT: b.ls .Ltmp2
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; CHECK-NEXT: orr x16, x0, #0xf
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; CHECK-NEXT: ldrb w16, [x16]
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; CHECK-NEXT: cmp x16, x0, lsr #56
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; CHECK-NEXT: b.eq .Ltmp1
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; CHECK-NEXT: .Ltmp2:
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; CHECK-NEXT: stp x0, x1, [sp, #-256]!
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; CHECK-NEXT: stp x29, x30, [sp, #232]
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; CHECK-NEXT: mov x1, #456
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@ -58,9 +70,21 @@ declare void @llvm.hwasan.check.memaccess(i8*, i8*, i32)
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; CHECK-NEXT: ubfx x16, x1, #4, #52
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; CHECK-NEXT: ldrb w16, [x9, x16]
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; CHECK-NEXT: cmp x16, x1, lsr #56
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; CHECK-NEXT: b.ne .Ltmp1
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; CHECK-NEXT: b.ne .Ltmp3
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; CHECK-NEXT: .Ltmp4:
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; CHECK-NEXT: ret
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; CHECK-NEXT: .Ltmp1:
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; CHECK-NEXT: .Ltmp3:
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; CHECK-NEXT: cmp w16, #15
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; CHECK-NEXT: b.hi .Ltmp5
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; CHECK-NEXT: and x17, x1, #0xf
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; CHECK-NEXT: add x17, x17, #2047
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; CHECK-NEXT: cmp w16, w17
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; CHECK-NEXT: b.ls .Ltmp5
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; CHECK-NEXT: orr x16, x1, #0xf
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; CHECK-NEXT: ldrb w16, [x16]
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; CHECK-NEXT: cmp x16, x1, lsr #56
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; CHECK-NEXT: b.eq .Ltmp4
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; CHECK-NEXT: .Ltmp5:
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; CHECK-NEXT: stp x0, x1, [sp, #-256]!
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; CHECK-NEXT: stp x29, x30, [sp, #232]
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; CHECK-NEXT: mov x0, x1
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@ -9,9 +9,10 @@ declare void @use32(i32*)
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define void @test_alloca() sanitize_hwaddress {
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; CHECK-LABEL: @test_alloca(
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; CHECK: %[[GEP:[^ ]*]] = getelementptr { i32, [12 x i8] }, { i32, [12 x i8] }* %x, i32 0, i32 0
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; CHECK: %[[T1:[^ ]*]] = call i8 @__hwasan_generate_tag()
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; CHECK: %[[A:[^ ]*]] = zext i8 %[[T1]] to i64
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; CHECK: %[[B:[^ ]*]] = ptrtoint i32* %x to i64
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; CHECK: %[[B:[^ ]*]] = ptrtoint i32* %[[GEP]] to i64
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; CHECK: %[[C:[^ ]*]] = shl i64 %[[A]], 56
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; CHECK: or i64 %[[B]], %[[C]]
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@ -16,24 +16,29 @@ define void @test_alloca() sanitize_hwaddress {
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; CHECK: %[[B:[^ ]*]] = lshr i64 %[[A]], 20
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; CHECK: %[[BASE_TAG:[^ ]*]] = xor i64 %[[A]], %[[B]]
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; CHECK: %[[X:[^ ]*]] = alloca i32, align 16
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; CHECK: %[[X:[^ ]*]] = alloca { i32, [12 x i8] }, align 16
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; CHECK: %[[X_GEP:[^ ]*]] = getelementptr { i32, [12 x i8] }, { i32, [12 x i8] }* %[[X]], i32 0, i32 0
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; CHECK: %[[X_TAG:[^ ]*]] = xor i64 %[[BASE_TAG]], 0
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; CHECK: %[[X1:[^ ]*]] = ptrtoint i32* %[[X]] to i64
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; CHECK: %[[X1:[^ ]*]] = ptrtoint i32* %[[X_GEP]] to i64
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; CHECK: %[[C:[^ ]*]] = shl i64 %[[X_TAG]], 56
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; CHECK: %[[D:[^ ]*]] = or i64 %[[X1]], %[[C]]
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; CHECK: %[[X_HWASAN:[^ ]*]] = inttoptr i64 %[[D]] to i32*
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; CHECK: %[[X_TAG2:[^ ]*]] = trunc i64 %[[X_TAG]] to i8
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; CHECK: %[[E:[^ ]*]] = ptrtoint i32* %[[X]] to i64
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; CHECK: %[[E:[^ ]*]] = ptrtoint i32* %[[X_GEP]] to i64
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; CHECK: %[[F:[^ ]*]] = lshr i64 %[[E]], 4
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; DYNAMIC-SHADOW: %[[X_SHADOW:[^ ]*]] = getelementptr i8, i8* %.hwasan.shadow, i64 %[[F]]
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; ZERO-BASED-SHADOW: %[[X_SHADOW:[^ ]*]] = inttoptr i64 %[[F]] to i8*
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; CHECK: call void @llvm.memset.p0i8.i64(i8* align 1 %[[X_SHADOW]], i8 %[[X_TAG2]], i64 1, i1 false)
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; CHECK: %[[X_SHADOW_GEP:[^ ]*]] = getelementptr i8, i8* %[[X_SHADOW]], i32 0
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; CHECK: store i8 4, i8* %[[X_SHADOW_GEP]]
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; CHECK: %[[X_I8:[^ ]*]] = bitcast i32* %[[X_GEP]] to i8*
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; CHECK: %[[X_I8_GEP:[^ ]*]] = getelementptr i8, i8* %[[X_I8]], i32 15
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; CHECK: store i8 %[[X_TAG2]], i8* %[[X_I8_GEP]]
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; CHECK: call void @use32(i32* nonnull %[[X_HWASAN]])
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; UAR-TAGS: %[[BASE_TAG_COMPL:[^ ]*]] = xor i64 %[[BASE_TAG]], 255
|
||||
; UAR-TAGS: %[[X_TAG_UAR:[^ ]*]] = trunc i64 %[[BASE_TAG_COMPL]] to i8
|
||||
; CHECK: %[[E2:[^ ]*]] = ptrtoint i32* %[[X]] to i64
|
||||
; CHECK: %[[E2:[^ ]*]] = ptrtoint i32* %[[X_GEP]] to i64
|
||||
; CHECK: %[[F2:[^ ]*]] = lshr i64 %[[E2]], 4
|
||||
; DYNAMIC-SHADOW: %[[X_SHADOW2:[^ ]*]] = getelementptr i8, i8* %.hwasan.shadow, i64 %[[F2]]
|
||||
; ZERO-BASED-SHADOW: %[[X_SHADOW2:[^ ]*]] = inttoptr i64 %[[F2]] to i8*
|
||||
|
||||
@ -27,11 +27,35 @@ define i8 @test_load8(i8* %a) sanitize_hwaddress {
|
||||
; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to i8*
|
||||
; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, i8* %[[E]]
|
||||
; RECOVER: %[[F:[^ ]*]] = icmp ne i8 %[[PTRTAG]], %[[MEMTAG]]
|
||||
; RECOVER: br i1 %[[F]], label {{.*}}, label {{.*}}, !prof {{.*}}
|
||||
; RECOVER: br i1 %[[F]], label %[[MISMATCH:[0-9]*]], label %[[CONT:[0-9]*]], !prof {{.*}}
|
||||
|
||||
; RECOVER: [[MISMATCH]]:
|
||||
; RECOVER: %[[NOTSHORT:[^ ]*]] = icmp ugt i8 %[[MEMTAG]], 15
|
||||
; RECOVER: br i1 %[[NOTSHORT]], label %[[FAIL:[0-9]*]], label %[[SHORT:[0-9]*]], !prof {{.*}}
|
||||
|
||||
; RECOVER: [[FAIL]]:
|
||||
; RECOVER: call void asm sideeffect "brk #2336", "{x0}"(i64 %[[A]])
|
||||
; RECOVER: br label
|
||||
|
||||
; RECOVER: [[SHORT]]:
|
||||
; RECOVER: %[[LOWBITS:[^ ]*]] = and i64 %[[A]], 15
|
||||
; RECOVER: %[[LOWBITS_I8:[^ ]*]] = trunc i64 %[[LOWBITS]] to i8
|
||||
; RECOVER: %[[LAST:[^ ]*]] = add i8 %[[LOWBITS_I8]], 0
|
||||
; RECOVER: %[[OOB:[^ ]*]] = icmp uge i8 %[[LAST]], %[[MEMTAG]]
|
||||
; RECOVER: br i1 %[[OOB]], label %[[FAIL]], label %[[INBOUNDS:[0-9]*]], !prof {{.*}}
|
||||
|
||||
; RECOVER: [[INBOUNDS]]:
|
||||
; RECOVER: %[[EOG_ADDR:[^ ]*]] = or i64 %[[C]], 15
|
||||
; RECOVER: %[[EOG_PTR:[^ ]*]] = inttoptr i64 %[[EOG_ADDR]] to i8*
|
||||
; RECOVER: %[[EOGTAG:[^ ]*]] = load i8, i8* %[[EOG_PTR]]
|
||||
; RECOVER: %[[EOG_MISMATCH:[^ ]*]] = icmp ne i8 %[[PTRTAG]], %[[EOGTAG]]
|
||||
; RECOVER: br i1 %[[EOG_MISMATCH]], label %[[FAIL]], label %[[CONT1:[0-9]*]], !prof {{.*}}
|
||||
|
||||
; RECOVER: [[CONT1]]:
|
||||
; RECOVER: br label %[[CONT]]
|
||||
|
||||
; RECOVER: [[CONT]]:
|
||||
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess(i8* %.hwasan.shadow, i8* %a, i32 0)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess(i8* null, i8* %a, i32 0)
|
||||
|
||||
@ -54,11 +78,35 @@ define i16 @test_load16(i16* %a) sanitize_hwaddress {
|
||||
; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to i8*
|
||||
; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, i8* %[[E]]
|
||||
; RECOVER: %[[F:[^ ]*]] = icmp ne i8 %[[PTRTAG]], %[[MEMTAG]]
|
||||
; RECOVER: br i1 %[[F]], label {{.*}}, label {{.*}}, !prof {{.*}}
|
||||
; RECOVER: br i1 %[[F]], label %[[MISMATCH:[0-9]*]], label %[[CONT:[0-9]*]], !prof {{.*}}
|
||||
|
||||
; RECOVER: [[MISMATCH]]:
|
||||
; RECOVER: %[[NOTSHORT:[^ ]*]] = icmp ugt i8 %[[MEMTAG]], 15
|
||||
; RECOVER: br i1 %[[NOTSHORT]], label %[[FAIL:[0-9]*]], label %[[SHORT:[0-9]*]], !prof {{.*}}
|
||||
|
||||
; RECOVER: [[FAIL]]:
|
||||
; RECOVER: call void asm sideeffect "brk #2337", "{x0}"(i64 %[[A]])
|
||||
; RECOVER: br label
|
||||
|
||||
; RECOVER: [[SHORT]]:
|
||||
; RECOVER: %[[LOWBITS:[^ ]*]] = and i64 %[[A]], 15
|
||||
; RECOVER: %[[LOWBITS_I8:[^ ]*]] = trunc i64 %[[LOWBITS]] to i8
|
||||
; RECOVER: %[[LAST:[^ ]*]] = add i8 %[[LOWBITS_I8]], 1
|
||||
; RECOVER: %[[OOB:[^ ]*]] = icmp uge i8 %[[LAST]], %[[MEMTAG]]
|
||||
; RECOVER: br i1 %[[OOB]], label %[[FAIL]], label %[[INBOUNDS:[0-9]*]], !prof {{.*}}
|
||||
|
||||
; RECOVER: [[INBOUNDS]]:
|
||||
; RECOVER: %[[EOG_ADDR:[^ ]*]] = or i64 %[[C]], 15
|
||||
; RECOVER: %[[EOG_PTR:[^ ]*]] = inttoptr i64 %[[EOG_ADDR]] to i8*
|
||||
; RECOVER: %[[EOGTAG:[^ ]*]] = load i8, i8* %[[EOG_PTR]]
|
||||
; RECOVER: %[[EOG_MISMATCH:[^ ]*]] = icmp ne i8 %[[PTRTAG]], %[[EOGTAG]]
|
||||
; RECOVER: br i1 %[[EOG_MISMATCH]], label %[[FAIL]], label %[[CONT1:[0-9]*]], !prof {{.*}}
|
||||
|
||||
; RECOVER: [[CONT1]]:
|
||||
; RECOVER: br label %[[CONT]]
|
||||
|
||||
; RECOVER: [[CONT]]:
|
||||
|
||||
; ABORT: %[[A:[^ ]*]] = bitcast i16* %a to i8*
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess(i8* %.hwasan.shadow, i8* %[[A]], i32 1)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess(i8* null, i8* %[[A]], i32 1)
|
||||
|
||||
@ -14,9 +14,10 @@ define void @test_alloca() sanitize_hwaddress {
|
||||
; CHECK: %[[B:[^ ]*]] = lshr i64 %[[A]], 20
|
||||
; CHECK: %[[BASE_TAG:[^ ]*]] = xor i64 %[[A]], %[[B]]
|
||||
|
||||
; CHECK: %[[X:[^ ]*]] = alloca i32, align 16
|
||||
; CHECK: %[[X:[^ ]*]] = alloca { i32, [12 x i8] }, align 16
|
||||
; CHECK: %[[X_GEP:[^ ]*]] = getelementptr { i32, [12 x i8] }, { i32, [12 x i8] }* %[[X]], i32 0, i32 0
|
||||
; CHECK: %[[X_TAG:[^ ]*]] = xor i64 %[[BASE_TAG]], 0
|
||||
; CHECK: %[[X1:[^ ]*]] = ptrtoint i32* %[[X]] to i64
|
||||
; CHECK: %[[X1:[^ ]*]] = ptrtoint i32* %[[X_GEP]] to i64
|
||||
; CHECK: %[[C:[^ ]*]] = shl i64 %[[X_TAG]], 56
|
||||
; CHECK: %[[D:[^ ]*]] = or i64 %[[C]], 72057594037927935
|
||||
; CHECK: %[[E:[^ ]*]] = and i64 %[[X1]], %[[D]]
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user