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[ARMv8] Implement the NEON instructions VRINT{N, X, A, Z, M, P}.
llvm-svn: 186688
This commit is contained in:
Joey Gouly
parent
8ae3d3dbfc
commit
cfa16b3bc1
@ -364,6 +364,14 @@ def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
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def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
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def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
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// Vector Rounding
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def int_arm_neon_vrintn : Neon_1Arg_Intrinsic;
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def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
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def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
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def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
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def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
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def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
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// De-interleaving vector loads from N-element structures.
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// Source operands are the address and alignment.
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def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
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@ -5738,6 +5738,34 @@ def VTBX4Pseudo
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IIC_VTBX4, "$orig = $dst", []>;
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} // DecoderMethod = "DecodeTBLInstruction"
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// VRINT : Vector Rounding
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multiclass VRINT_FPI<string op, bits<3> op9_7, SDPatternOperator Int> {
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let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
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def D : N2VDIntnp<0b10, 0b100, 0, NoItinerary,
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!strconcat("vrint", op), "f32",
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v2f32, v2f32, Int>, Requires<[HasV8, HasNEON]> {
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let Inst{9-7} = op9_7;
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}
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def Q : N2VQIntnp<0b10, 0b100, 0, NoItinerary,
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!strconcat("vrint", op), "f32",
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v4f32, v4f32, Int>, Requires<[HasV8, HasNEON]> {
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let Inst{9-7} = op9_7;
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}
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}
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def : InstAlias<!strconcat("vrint", op, ".f32.f32\t$Dd, $Dm"),
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(!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>;
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def : InstAlias<!strconcat("vrint", op, ".f32.f32\t$Qd, $Qm"),
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(!cast<Instruction>(NAME#"Q") QPR:$Qd, QPR:$Qm)>;
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}
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defm VRINTNN : VRINT_FPI<"n", 0b000, int_arm_neon_vrintn>;
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defm VRINTXN : VRINT_FPI<"x", 0b001, int_arm_neon_vrintx>;
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defm VRINTAN : VRINT_FPI<"a", 0b010, int_arm_neon_vrinta>;
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defm VRINTZN : VRINT_FPI<"z", 0b011, int_arm_neon_vrintz>;
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defm VRINTMN : VRINT_FPI<"m", 0b101, int_arm_neon_vrintm>;
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defm VRINTPN : VRINT_FPI<"p", 0b111, int_arm_neon_vrintp>;
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//===----------------------------------------------------------------------===//
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// NEON instructions for single-precision FP math
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//===----------------------------------------------------------------------===//
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@ -263,6 +263,8 @@ class ARMAsmParser : public MCTargetAsmParser {
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const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
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bool shouldOmitCCOutOperand(StringRef Mnemonic,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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bool shouldOmitPredicateOperand(StringRef Mnemonic,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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public:
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enum ARMMatchResultTy {
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@ -5157,6 +5159,25 @@ bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
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return false;
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}
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bool ARMAsmParser::shouldOmitPredicateOperand(
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StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
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// VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
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unsigned RegIdx = 3;
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if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
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static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
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if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
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static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
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RegIdx = 4;
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if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
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(ARMMCRegisterClasses[ARM::DPRRegClassID]
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.contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
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ARMMCRegisterClasses[ARM::QPRRegClassID]
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.contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
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return true;
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}
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}
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static bool isDataTypeToken(StringRef Tok) {
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return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
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Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
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@ -5359,6 +5380,15 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
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delete Op;
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}
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// Some instructions have the same mnemonic, but don't always
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// have a predicate. Distinguish them here and delete the
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// predicate if needed.
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if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
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ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
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Operands.erase(Operands.begin() + 1);
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delete Op;
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}
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// ARM mode 'blx' need special handling, as the register operand version
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// is predicable, but the label operand version is not. So, we can't rely
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// on the Mnemonic based checking to correctly figure out when to put
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@ -44,3 +44,40 @@ vcvtp.s32.f32 q4, q15
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@ CHECK: vcvtp.s32.f32 q4, q15 @ encoding: [0x6e,0x82,0xbb,0xf3]
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vcvtp.u32.f32 q9, q8
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@ CHECK: vcvtp.u32.f32 q9, q8 @ encoding: [0xe0,0x22,0xfb,0xf3]
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vrintn.f32 d3, d0
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@ CHECK: vrintn.f32 d3, d0 @ encoding: [0x00,0x34,0xba,0xf3]
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vrintn.f32 q1, q4
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@ CHECK: vrintn.f32 q1, q4 @ encoding: [0x48,0x24,0xba,0xf3]
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vrintx.f32 d5, d12
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@ CHECK: vrintx.f32 d5, d12 @ encoding: [0x8c,0x54,0xba,0xf3]
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vrintx.f32 q0, q3
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@ CHECK: vrintx.f32 q0, q3 @ encoding: [0xc6,0x04,0xba,0xf3]
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vrinta.f32 d3, d0
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@ CHECK: vrinta.f32 d3, d0 @ encoding: [0x00,0x35,0xba,0xf3]
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vrinta.f32 q8, q2
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@ CHECK: vrinta.f32 q8, q2 @ encoding: [0x44,0x05,0xfa,0xf3]
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vrintz.f32 d12, d18
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@ CHECK: vrintz.f32 d12, d18 @ encoding: [0xa2,0xc5,0xba,0xf3]
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vrintz.f32 q9, q4
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@ CHECK: vrintz.f32 q9, q4 @ encoding: [0xc8,0x25,0xfa,0xf3]
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vrintm.f32 d3, d0
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@ CHECK: vrintm.f32 d3, d0 @ encoding: [0x80,0x36,0xba,0xf3]
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vrintm.f32 q1, q4
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@ CHECK: vrintm.f32 q1, q4 @ encoding: [0xc8,0x26,0xba,0xf3]
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vrintp.f32 d3, d0
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@ CHECK: vrintp.f32 d3, d0 @ encoding: [0x80,0x37,0xba,0xf3]
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vrintp.f32 q1, q4
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@ CHECK: vrintp.f32 q1, q4 @ encoding: [0xc8,0x27,0xba,0xf3]
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@ test the aliases of vrint
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vrintn.f32.f32 d3, d0
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@ CHECK: vrintn.f32 d3, d0 @ encoding: [0x00,0x34,0xba,0xf3]
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vrintx.f32.f32 q0, q3
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@ CHECK: vrintx.f32 q0, q3 @ encoding: [0xc6,0x04,0xba,0xf3]
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vrinta.f32.f32 d3, d0
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@ CHECK: vrinta.f32 d3, d0 @ encoding: [0x00,0x35,0xba,0xf3]
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vrintz.f32.f32 q9, q4
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@ CHECK: vrintz.f32 q9, q4 @ encoding: [0xc8,0x25,0xfa,0xf3]
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vrintp.f32.f32 q1, q4
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@ CHECK: vrintp.f32 q1, q4 @ encoding: [0xc8,0x27,0xba,0xf3]
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@ -44,3 +44,40 @@ vcvtp.s32.f32 q4, q15
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@ CHECK: vcvtp.s32.f32 q4, q15 @ encoding: [0xbb,0xff,0x6e,0x82]
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vcvtp.u32.f32 q9, q8
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@ CHECK: vcvtp.u32.f32 q9, q8 @ encoding: [0xfb,0xff,0xe0,0x22]
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vrintn.f32 d3, d0
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@ CHECK: vrintn.f32 d3, d0 @ encoding: [0xba,0xff,0x00,0x34]
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vrintn.f32 q1, q4
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@ CHECK: vrintn.f32 q1, q4 @ encoding: [0xba,0xff,0x48,0x24]
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vrintx.f32 d5, d12
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@ CHECK: vrintx.f32 d5, d12 @ encoding: [0xba,0xff,0x8c,0x54]
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vrintx.f32 q0, q3
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@ CHECK: vrintx.f32 q0, q3 @ encoding: [0xba,0xff,0xc6,0x04]
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vrinta.f32 d3, d0
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@ CHECK: vrinta.f32 d3, d0 @ encoding: [0xba,0xff,0x00,0x35]
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vrinta.f32 q8, q2
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@ CHECK: vrinta.f32 q8, q2 @ encoding: [0xfa,0xff,0x44,0x05]
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vrintz.f32 d12, d18
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@ CHECK: vrintz.f32 d12, d18 @ encoding: [0xba,0xff,0xa2,0xc5]
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vrintz.f32 q9, q4
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@ CHECK: vrintz.f32 q9, q4 @ encoding: [0xfa,0xff,0xc8,0x25]
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vrintm.f32 d3, d0
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@ CHECK: vrintm.f32 d3, d0 @ encoding: [0xba,0xff,0x80,0x36]
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vrintm.f32 q1, q4
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@ CHECK: vrintm.f32 q1, q4 @ encoding: [0xba,0xff,0xc8,0x26]
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vrintp.f32 d3, d0
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@ CHECK: vrintp.f32 d3, d0 @ encoding: [0xba,0xff,0x80,0x37]
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vrintp.f32 q1, q4
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@ CHECK: vrintp.f32 q1, q4 @ encoding: [0xba,0xff,0xc8,0x27]
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@ test the aliases of vrint
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vrintn.f32.f32 d3, d0
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@ CHECK: vrintn.f32 d3, d0 @ encoding: [0xba,0xff,0x00,0x34]
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vrintx.f32.f32 q0, q3
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@ CHECK: vrintx.f32 q0, q3 @ encoding: [0xba,0xff,0xc6,0x04]
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vrinta.f32.f32 d3, d0
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@ CHECK: vrinta.f32 d3, d0 @ encoding: [0xba,0xff,0x00,0x35]
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vrintz.f32.f32 q9, q4
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@ CHECK: vrintz.f32 q9, q4 @ encoding: [0xfa,0xff,0xc8,0x25]
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vrintp.f32.f32 q1, q4
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@ CHECK: vrintp.f32 q1, q4 @ encoding: [0xba,0xff,0xc8,0x27]
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@ -44,3 +44,28 @@
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# CHECK: vcvtp.s32.f32 q4, q15
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0xe0 0x22 0xfb 0xf3
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# CHECK: vcvtp.u32.f32 q9, q8
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0x00 0x34 0xba 0xf3
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# CHECK: vrintn.f32 d3, d0
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0x48 0x24 0xba 0xf3
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# CHECK: vrintn.f32 q1, q4
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0x8c 0x54 0xba 0xf3
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# CHECK: vrintx.f32 d5, d12
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0xc6 0x04 0xba 0xf3
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# CHECK: vrintx.f32 q0, q3
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0x00 0x35 0xba 0xf3
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# CHECK: vrinta.f32 d3, d0
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0x44 0x05 0xfa 0xf3
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# CHECK: vrinta.f32 q8, q2
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0xa2 0xc5 0xba 0xf3
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# CHECK: vrintz.f32 d12, d18
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0xc8 0x25 0xfa 0xf3
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# CHECK: vrintz.f32 q9, q4
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0x80 0x36 0xba 0xf3
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# CHECK: vrintm.f32 d3, d0
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0xc8 0x26 0xba 0xf3
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# CHECK: vrintm.f32 q1, q4
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0x80 0x37 0xba 0xf3
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# CHECK: vrintp.f32 d3, d0
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0xc8 0x27 0xba 0xf3
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# CHECK: vrintp.f32 q1, q4
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@ -44,3 +44,28 @@
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# CHECK: vcvtp.s32.f32 q4, q15
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0xfb 0xff 0xe0 0x22
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# CHECK: vcvtp.u32.f32 q9, q8
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0xba 0xff 0x00 0x34
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# CHECK: vrintn.f32 d3, d0
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0xba 0xff 0x48 0x24
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# CHECK: vrintn.f32 q1, q4
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0xba 0xff 0x8c 0x54
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# CHECK: vrintx.f32 d5, d12
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0xba 0xff 0xc6 0x04
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# CHECK: vrintx.f32 q0, q3
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0xba 0xff 0x00 0x35
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# CHECK: vrinta.f32 d3, d0
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0xfa 0xff 0x44 0x05
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# CHECK: vrinta.f32 q8, q2
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0xba 0xff 0xa2 0xc5
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# CHECK: vrintz.f32 d12, d18
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0xfa 0xff 0xc8 0x25
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# CHECK: vrintz.f32 q9, q4
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0xba 0xff 0x80 0x36
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# CHECK: vrintm.f32 d3, d0
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0xba 0xff 0xc8 0x26
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# CHECK: vrintm.f32 q1, q4
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0xba 0xff 0x80 0x37
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# CHECK: vrintp.f32 d3, d0
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0xba 0xff 0xc8 0x27
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# CHECK: vrintp.f32 q1, q4
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