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Support generating machine instructions for Phi nodes (based on x86, but with
modifications for 1 LLVM BB --> many MBBs). Fix store operand order: make it always be Base, Offset, SrcReg (think "[ Base + Offset ] = SrcReg"). Rewrite visitBranchInst() to be even dumber (but working) -- give up on the branch fallthrough trick, for the time being. Make visitSetCondInst() work. llvm-svn: 14208
This commit is contained in:
Brian Gaeke
parent
af2408a4ee
commit
d084a534a2
@ -13,6 +13,7 @@
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#include "SparcV8.h"
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#include "SparcV8InstrInfo.h"
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#include "Support/Debug.h"
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#include "llvm/Instructions.h"
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#include "llvm/IntrinsicLowering.h"
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#include "llvm/Pass.h"
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@ -92,6 +93,12 @@ namespace {
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void LoadArgumentsToVirtualRegs(Function *F);
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/// SelectPHINodes - Insert machine code to generate phis. This is tricky
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/// because we have to generate our sources into the source basic blocks,
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/// not the current one.
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///
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void SelectPHINodes();
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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///
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@ -303,6 +310,102 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *F) {
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}
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}
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void V8ISel::SelectPHINodes() {
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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const Function &LF = *F->getFunction(); // The LLVM function...
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for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
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const BasicBlock *BB = I;
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MachineBasicBlock &MBB = *MBBMap[I];
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// Loop over all of the PHI nodes in the LLVM basic block...
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MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
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for (BasicBlock::const_iterator I = BB->begin();
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PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
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// Create a new machine instr PHI node, and insert it.
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unsigned PHIReg = getReg(*PN);
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MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
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V8::PHI, PN->getNumOperands(), PHIReg);
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MachineInstr *LongPhiMI = 0;
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if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
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LongPhiMI = BuildMI(MBB, PHIInsertPoint,
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V8::PHI, PN->getNumOperands(), PHIReg+1);
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// PHIValues - Map of blocks to incoming virtual registers. We use this
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// so that we only initialize one incoming value for a particular block,
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// even if the block has multiple entries in the PHI node.
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//
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std::map<MachineBasicBlock*, unsigned> PHIValues;
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for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
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MachineBasicBlock *PredMBB = 0;
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for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin (),
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PE = MBB.pred_end (); PI != PE; ++PI)
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if (PN->getIncomingBlock(i) == (*PI)->getBasicBlock()) {
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PredMBB = *PI;
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break;
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}
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assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
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unsigned ValReg;
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std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
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PHIValues.lower_bound(PredMBB);
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if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
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// We already inserted an initialization of the register for this
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// predecessor. Recycle it.
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ValReg = EntryIt->second;
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} else {
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// Get the incoming value into a virtual register.
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//
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Value *Val = PN->getIncomingValue(i);
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// If this is a constant or GlobalValue, we may have to insert code
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// into the basic block to compute it into a virtual register.
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if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
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isa<GlobalValue>(Val)) {
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// Simple constants get emitted at the end of the basic block,
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// before any terminator instructions. We "know" that the code to
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// move a constant into a register will never clobber any flags.
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ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
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} else {
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// Because we don't want to clobber any values which might be in
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// physical registers with the computation of this constant (which
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// might be arbitrarily complex if it is a constant expression),
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// just insert the computation at the top of the basic block.
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MachineBasicBlock::iterator PI = PredMBB->begin();
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// Skip over any PHI nodes though!
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while (PI != PredMBB->end() && PI->getOpcode() == V8::PHI)
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++PI;
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ValReg = getReg(Val, PredMBB, PI);
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}
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// Remember that we inserted a value for this PHI for this predecessor
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PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
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}
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PhiMI->addRegOperand(ValReg);
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PhiMI->addMachineBasicBlockOperand(PredMBB);
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if (LongPhiMI) {
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LongPhiMI->addRegOperand(ValReg+1);
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LongPhiMI->addMachineBasicBlockOperand(PredMBB);
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}
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}
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// Now that we emitted all of the incoming values for the PHI node, make
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// sure to reposition the InsertPoint after the PHI that we just added.
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// This is needed because we might have inserted a constant into this
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// block, right after the PHI's which is before the old insert point!
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PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
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++PHIInsertPoint;
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}
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}
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}
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bool V8ISel::runOnFunction(Function &Fn) {
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// First pass over the function, lower any unknown intrinsic functions
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// with the IntrinsicLowering class.
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@ -327,7 +430,7 @@ bool V8ISel::runOnFunction(Function &Fn) {
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visit(Fn);
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// Select the PHI nodes
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//SelectPHINodes();
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SelectPHINodes();
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RegMap.clear();
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MBBMap.clear();
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@ -421,16 +524,16 @@ void V8ISel::visitStoreInst(StoreInst &I) {
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unsigned PtrReg = getReg (I.getOperand (1));
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switch (getClassB (SrcVal->getType ())) {
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case cByte:
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BuildMI (BB, V8::STBrm, 1, SrcReg).addReg (PtrReg).addSImm(0);
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BuildMI (BB, V8::STBrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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return;
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case cShort:
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BuildMI (BB, V8::STHrm, 1, SrcReg).addReg (PtrReg).addSImm(0);
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BuildMI (BB, V8::STHrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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return;
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case cInt:
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BuildMI (BB, V8::STrm, 1, SrcReg).addReg (PtrReg).addSImm(0);
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BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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return;
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case cLong:
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BuildMI (BB, V8::STDrm, 1, SrcReg).addReg (PtrReg).addSImm(0);
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BuildMI (BB, V8::STDrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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return;
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default:
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std::cerr << "Store instruction not handled: " << I;
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@ -499,32 +602,22 @@ static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
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/// visitBranchInst - Handles conditional and unconditional branches.
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///
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void V8ISel::visitBranchInst(BranchInst &I) {
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// Update machine-CFG edges
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BB->addSuccessor (MBBMap[I.getSuccessor(0)]);
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if (I.isConditional())
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BB->addSuccessor (MBBMap[I.getSuccessor(1)]);
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BasicBlock *NextBB = getBlockAfter(I.getParent()); // BB after current one
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BasicBlock *takenSucc = I.getSuccessor (0);
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if (!I.isConditional()) { // Unconditional branch?
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if (I.getSuccessor(0) != NextBB)
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BuildMI (BB, V8::BA, 1).addMBB (MBBMap[takenSucc]);
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return;
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}
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MachineBasicBlock *takenSuccMBB = MBBMap[takenSucc];
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BB->addSuccessor (takenSuccMBB);
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if (I.isConditional()) { // conditional branch
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BasicBlock *notTakenSucc = I.getSuccessor (1);
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MachineBasicBlock *notTakenSuccMBB = MBBMap[notTakenSucc];
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BB->addSuccessor (notTakenSuccMBB);
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unsigned CondReg = getReg (I.getCondition ());
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BasicBlock *notTakenSucc = I.getSuccessor (1);
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// Set Z condition code if CondReg was false
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BuildMI (BB, V8::CMPri, 2).addSImm (0).addReg (CondReg);
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if (notTakenSucc == NextBB) {
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if (takenSucc != NextBB)
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BuildMI (BB, V8::BNE, 1).addMBB (MBBMap[takenSucc]);
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} else {
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BuildMI (BB, V8::BE, 1).addMBB (MBBMap[notTakenSucc]);
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if (takenSucc != NextBB)
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BuildMI (BB, V8::BA, 1).addMBB (MBBMap[takenSucc]);
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// CondReg=(<condition>);
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// If (CondReg==0) goto notTakenSuccMBB;
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unsigned CondReg = getReg (I.getCondition ());
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BuildMI (BB, V8::CMPri, 2).addSImm (0).addReg (CondReg);
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BuildMI (BB, V8::BE, 1).addMBB (notTakenSuccMBB);
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}
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// goto takenSuccMBB;
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BuildMI (BB, V8::BA, 1).addMBB (takenSuccMBB);
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}
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/// emitGEPOperation - Common code shared between visitGetElementPtrInst and
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@ -714,29 +807,62 @@ void V8ISel::visitSetCondInst(Instruction &I) {
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V8::BLEU, V8::BLE, // setle = bleu ble
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V8::BCC, V8::BGE // setge = bcc bge
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};
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unsigned Opcode = OpcodeTab[BranchIdx + (Ty->isSigned() ? 1 : 0)];
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MachineBasicBlock *Copy1MBB, *Copy0MBB, *CopyCondMBB;
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MachineBasicBlock::iterator IP;
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#if 0
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// Cond. Branch from BB --> either Copy1MBB or Copy0MBB --> CopyCondMBB
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// Then once we're done with the SetCC, BB = CopyCondMBB.
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BasicBlock *LLVM_BB = BB.getBasicBlock ();
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unsigned Cond0Reg = makeAnotherReg (I.getType ());
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unsigned Cond1Reg = makeAnotherReg (I.getType ());
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F->getBasicBlockList ().push_back (Copy1MBB = new MachineBasicBlock (LLVM_BB));
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F->getBasicBlockList ().push_back (Copy0MBB = new MachineBasicBlock (LLVM_BB));
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F->getBasicBlockList ().push_back (CopyCondMBB = new MachineBasicBlock (LLVM_BB));
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BuildMI (BB, Opcode, 1).addMBB (Copy1MBB);
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BuildMI (BB, V8::BA, 1).addMBB (Copy0MBB);
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IP = Copy1MBB->begin ();
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BuildMI (*Copy1MBB, IP, V8::ORri, 2, Cond1Reg).addZImm (1).addReg (V8::G0);
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BuildMI (*Copy1MBB, IP, V8::BA, 1).addMBB (CopyCondMBB);
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IP = Copy0MBB->begin ();
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BuildMI (*Copy0MBB, IP, V8::ORri, 2, Cond0Reg).addZImm (0).addReg (V8::G0);
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BuildMI (*Copy0MBB, IP, V8::BA, 1).addMBB (CopyCondMBB);
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// What should go in CopyCondMBB: PHI, then OR to copy cond. reg to DestReg
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#endif
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visitInstruction(I);
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unsigned Opcode = OpcodeTab[2*BranchIdx + (Ty->isSigned() ? 1 : 0)];
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MachineBasicBlock *thisMBB = BB;
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const BasicBlock *LLVM_BB = BB->getBasicBlock ();
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// thisMBB:
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// ...
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// subcc %reg0, %reg1, %g0
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// bCC copy1MBB
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// ba copy0MBB
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// FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
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// if we could insert other, non-terminator instructions after the
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// bCC. But MBB->getFirstTerminator() can't understand this.
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MachineBasicBlock *copy1MBB = new MachineBasicBlock (LLVM_BB);
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F->getBasicBlockList ().push_back (copy1MBB);
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BuildMI (BB, Opcode, 1).addMBB (copy1MBB);
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MachineBasicBlock *copy0MBB = new MachineBasicBlock (LLVM_BB);
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F->getBasicBlockList ().push_back (copy0MBB);
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BuildMI (BB, V8::BA, 1).addMBB (copy0MBB);
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// Update machine-CFG edges
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BB->addSuccessor (copy1MBB);
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BB->addSuccessor (copy0MBB);
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// copy0MBB:
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// %FalseValue = or %G0, 0
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// ba sinkMBB
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BB = copy0MBB;
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unsigned FalseValue = makeAnotherReg (I.getType ());
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BuildMI (BB, V8::ORri, 2, FalseValue).addReg (V8::G0).addZImm (0);
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MachineBasicBlock *sinkMBB = new MachineBasicBlock (LLVM_BB);
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F->getBasicBlockList ().push_back (sinkMBB);
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BuildMI (BB, V8::BA, 1).addMBB (sinkMBB);
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// Update machine-CFG edges
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BB->addSuccessor (sinkMBB);
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DEBUG (std::cerr << "thisMBB is at " << (void*)thisMBB << "\n");
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DEBUG (std::cerr << "copy1MBB is at " << (void*)copy1MBB << "\n");
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DEBUG (std::cerr << "copy0MBB is at " << (void*)copy0MBB << "\n");
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DEBUG (std::cerr << "sinkMBB is at " << (void*)sinkMBB << "\n");
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// copy1MBB:
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// %TrueValue = or %G0, 1
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// ba sinkMBB
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BB = copy1MBB;
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unsigned TrueValue = makeAnotherReg (I.getType ());
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BuildMI (BB, V8::ORri, 2, TrueValue).addReg (V8::G0).addZImm (1);
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BuildMI (BB, V8::BA, 1).addMBB (sinkMBB);
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// Update machine-CFG edges
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BB->addSuccessor (sinkMBB);
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// sinkMBB:
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
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// ...
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BB = sinkMBB;
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BuildMI (BB, V8::PHI, 4, DestReg).addReg (FalseValue)
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.addMBB (copy0MBB).addReg (TrueValue).addMBB (copy1MBB);
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}
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