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Make TargetInstrInfo::isPredicable take a const reference, NFC

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llvm-svn: 296901
This commit is contained in:
Krzysztof Parzyszek 2017-03-03 18:30:54 +00:00
parent df0432e5e2
commit d151d23d21
13 changed files with 17 additions and 17 deletions
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2
include/llvm/Target/TargetInstrInfo.h
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@ -1142,7 +1142,7 @@ public:
/// Return true if the specified instruction can be predicated.
/// By default, this returns true for every instruction with a
/// PredicateOperand.
virtual bool isPredicable(MachineInstr &MI) const {
virtual bool isPredicable(const MachineInstr &MI) const {
return MI.getDesc().isPredicable();
}

4
lib/Target/AMDGPU/R600InstrInfo.cpp
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@ -869,7 +869,7 @@ bool R600InstrInfo::isPredicated(const MachineInstr &MI) const {
}
}
bool R600InstrInfo::isPredicable(MachineInstr &MI) const {
bool R600InstrInfo::isPredicable(const MachineInstr &MI) const {
// XXX: KILL* instructions can be predicated, but they must be the last
// instruction in a clause, so this means any instructions after them cannot
// be predicated. Until we have proper support for instruction clauses in the
@ -880,7 +880,7 @@ bool R600InstrInfo::isPredicable(MachineInstr &MI) const {
} else if (MI.getOpcode() == AMDGPU::CF_ALU) {
// If the clause start in the middle of MBB then the MBB has more
// than a single clause, unable to predicate several clauses.
if (MI.getParent()->begin() != MachineBasicBlock::iterator(MI))
if (MI.getParent()->begin() != MachineBasicBlock::const_iterator(MI))
return false;
// TODO: We don't support KC merging atm
return MI.getOperand(3).getImm() == 0 && MI.getOperand(4).getImm() == 0;

2
lib/Target/AMDGPU/R600InstrInfo.h
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@ -177,7 +177,7 @@ public:
bool isPredicated(const MachineInstr &MI) const override;
bool isPredicable(MachineInstr &MI) const override;
bool isPredicable(const MachineInstr &MI) const override;
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
BranchProbability Probability) const override;

6
lib/Target/ARM/ARMBaseInstrInfo.cpp
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@ -597,7 +597,7 @@ static bool isEligibleForITBlock(const MachineInstr *MI) {
/// isPredicable - Return true if the specified instruction can be predicated.
/// By default, this returns true for every instruction with a
/// PredicateOperand.
bool ARMBaseInstrInfo::isPredicable(MachineInstr &MI) const {
bool ARMBaseInstrInfo::isPredicable(const MachineInstr &MI) const {
if (!MI.isPredicable())
return false;
@ -607,7 +607,7 @@ bool ARMBaseInstrInfo::isPredicable(MachineInstr &MI) const {
if (!isEligibleForITBlock(&MI))
return false;
ARMFunctionInfo *AFI =
const ARMFunctionInfo *AFI =
MI.getParent()->getParent()->getInfo<ARMFunctionInfo>();
if (AFI->isThumb2Function()) {
@ -623,7 +623,7 @@ bool ARMBaseInstrInfo::isPredicable(MachineInstr &MI) const {
namespace llvm {
template <> bool IsCPSRDead<MachineInstr>(MachineInstr *MI) {
template <> bool IsCPSRDead<MachineInstr>(const MachineInstr *MI) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || MO.isUndef() || MO.isUse())

2
lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -163,7 +163,7 @@ public:
bool DefinesPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred) const override;
bool isPredicable(MachineInstr &MI) const override;
bool isPredicable(const MachineInstr &MI) const override;
/// GetInstSize - Returns the size of the specified MachineInstr.
///

4
lib/Target/ARM/ARMFeatures.h
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@ -19,10 +19,10 @@
namespace llvm {
template<typename InstrType> // could be MachineInstr or MCInst
bool IsCPSRDead(InstrType *Instr);
bool IsCPSRDead(const InstrType *Instr);
template<typename InstrType> // could be MachineInstr or MCInst
inline bool isV8EligibleForIT(InstrType *Instr) {
inline bool isV8EligibleForIT(const InstrType *Instr) {
switch (Instr->getOpcode()) {
default:
return false;

2
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -8985,7 +8985,7 @@ unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
}
namespace llvm {
template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
template <> inline bool IsCPSRDead<MCInst>(const MCInst *Instr) {
return true; // In an assembly source, no need to second-guess
}
}

2
lib/Target/Hexagon/HexagonInstrInfo.cpp
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@ -1434,7 +1434,7 @@ bool HexagonInstrInfo::DefinesPredicate(
return false;
}
bool HexagonInstrInfo::isPredicable(MachineInstr &MI) const {
bool HexagonInstrInfo::isPredicable(const MachineInstr &MI) const {
return MI.getDesc().isPredicable();
}

2
lib/Target/Hexagon/HexagonInstrInfo.h
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@ -235,7 +235,7 @@ public:
/// Return true if the specified instruction can be predicated.
/// By default, this returns true for every instruction with a
/// PredicateOperand.
bool isPredicable(MachineInstr &MI) const override;
bool isPredicable(const MachineInstr &MI) const override;
/// Test if the given instruction should be considered a scheduling boundary.
/// This primarily includes labels and terminators.

2
lib/Target/PowerPC/PPCInstrInfo.cpp
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@ -1493,7 +1493,7 @@ bool PPCInstrInfo::DefinesPredicate(MachineInstr &MI,
return Found;
}
bool PPCInstrInfo::isPredicable(MachineInstr &MI) const {
bool PPCInstrInfo::isPredicable(const MachineInstr &MI) const {
unsigned OpC = MI.getOpcode();
switch (OpC) {
default:

2
lib/Target/PowerPC/PPCInstrInfo.h
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@ -253,7 +253,7 @@ public:
bool DefinesPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred) const override;
bool isPredicable(MachineInstr &MI) const override;
bool isPredicable(const MachineInstr &MI) const override;
// Comparison optimization.

2
lib/Target/SystemZ/SystemZInstrInfo.cpp
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@ -727,7 +727,7 @@ bool SystemZInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
return true;
}
bool SystemZInstrInfo::isPredicable(MachineInstr &MI) const {
bool SystemZInstrInfo::isPredicable(const MachineInstr &MI) const {
unsigned Opcode = MI.getOpcode();
if (Opcode == SystemZ::Return ||
Opcode == SystemZ::Trap ||

2
lib/Target/SystemZ/SystemZInstrInfo.h
View File

@ -215,7 +215,7 @@ public:
unsigned FalseReg) const override;
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
MachineRegisterInfo *MRI) const override;
bool isPredicable(MachineInstr &MI) const override;
bool isPredicable(const MachineInstr &MI) const override;
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
unsigned ExtraPredCycles,
BranchProbability Probability) const override;