mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-12-16 08:08:01 +00:00
Optimize a couple of common patterns involving conditional moves where the false
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g.
cmp r9, r4
mov r4, #0
moveq r4, #1
orr lr, lr, r4
should be:
cmp r9, r4
orreq lr, lr, #1
That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend
this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y).
It's possible to extend this to ADD and SUB but I don't think they are common.
rdar://8659097
llvm-svn: 151224
This commit is contained in:
Evan Cheng
parent
7888265c63
commit
d18a688213
@ -244,6 +244,7 @@ private:
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/// SelectCMOVOp - Select CMOV instructions for ARM.
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SDNode *SelectCMOVOp(SDNode *N);
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SDNode *SelectConditionalOp(SDNode *N);
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SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR,
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SDValue InFlag);
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@ -2302,9 +2303,6 @@ SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
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// Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
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// Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
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// Pattern complexity = 18 cost = 1 size = 0
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SDValue CPTmp0;
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SDValue CPTmp1;
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SDValue CPTmp2;
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if (Subtarget->isThumb()) {
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SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
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CCVal, CCR, InFlag);
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@ -2377,6 +2375,116 @@ SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
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return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
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}
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SDNode *ARMDAGToDAGISel::SelectConditionalOp(SDNode *N) {
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EVT VT = N->getValueType(0);
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SDValue FalseVal = N->getOperand(0);
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SDValue TrueVal = N->getOperand(1);
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ARMCC::CondCodes CCVal =
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(ARMCC::CondCodes)cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
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SDValue CCR = N->getOperand(3);
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assert(CCR.getOpcode() == ISD::Register);
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SDValue InFlag = N->getOperand(4);
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SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
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SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
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if (Subtarget->isThumb()) {
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SDValue CPTmp0;
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SDValue CPTmp1;
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if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
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unsigned Opc;
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switch (N->getOpcode()) {
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default: llvm_unreachable("Unexpected node");
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case ARMISD::CAND: Opc = ARM::t2ANDCCrs; break;
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case ARMISD::COR: Opc = ARM::t2ORRCCrs; break;
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case ARMISD::CXOR: Opc = ARM::t2EORCCrs; break;
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}
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SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CC, CCR, Reg0, InFlag };
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return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 7);
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}
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ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
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if (T) {
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unsigned TrueImm = T->getZExtValue();
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if (is_t2_so_imm(TrueImm)) {
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unsigned Opc;
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switch (N->getOpcode()) {
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default: llvm_unreachable("Unexpected node");
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case ARMISD::CAND: Opc = ARM::t2ANDCCri; break;
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case ARMISD::COR: Opc = ARM::t2ORRCCri; break;
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case ARMISD::CXOR: Opc = ARM::t2EORCCri; break;
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}
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SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
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SDValue Ops[] = { FalseVal, True, CC, CCR, Reg0, InFlag };
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return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 6);
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}
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}
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unsigned Opc;
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switch (N->getOpcode()) {
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default: llvm_unreachable("Unexpected node");
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case ARMISD::CAND: Opc = ARM::t2ANDCCrr; break;
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case ARMISD::COR: Opc = ARM::t2ORRCCrr; break;
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case ARMISD::CXOR: Opc = ARM::t2EORCCrr; break;
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}
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SDValue Ops[] = { FalseVal, TrueVal, CC, CCR, Reg0, InFlag };
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return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 6);
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}
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SDValue CPTmp0;
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SDValue CPTmp1;
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SDValue CPTmp2;
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if (SelectImmShifterOperand(TrueVal, CPTmp0, CPTmp2)) {
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unsigned Opc;
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switch (N->getOpcode()) {
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default: llvm_unreachable("Unexpected node");
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case ARMISD::CAND: Opc = ARM::ANDCCrsi; break;
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case ARMISD::COR: Opc = ARM::ORRCCrsi; break;
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case ARMISD::CXOR: Opc = ARM::EORCCrsi; break;
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}
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SDValue Ops[] = { FalseVal, CPTmp0, CPTmp2, CC, CCR, Reg0, InFlag };
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return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 7);
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}
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if (SelectRegShifterOperand(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
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unsigned Opc;
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switch (N->getOpcode()) {
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default: llvm_unreachable("Unexpected node");
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case ARMISD::CAND: Opc = ARM::ANDCCrsr; break;
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case ARMISD::COR: Opc = ARM::ORRCCrsr; break;
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case ARMISD::CXOR: Opc = ARM::EORCCrsr; break;
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}
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SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, Reg0, InFlag };
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return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 8);
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}
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ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
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if (T) {
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unsigned TrueImm = T->getZExtValue();
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if (is_so_imm(TrueImm)) {
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unsigned Opc;
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switch (N->getOpcode()) {
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default: llvm_unreachable("Unexpected node");
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case ARMISD::CAND: Opc = ARM::ANDCCri; break;
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case ARMISD::COR: Opc = ARM::ORRCCri; break;
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case ARMISD::CXOR: Opc = ARM::EORCCri; break;
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}
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SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
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SDValue Ops[] = { FalseVal, True, CC, CCR, Reg0, InFlag };
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return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 6);
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}
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}
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unsigned Opc;
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switch (N->getOpcode()) {
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default: llvm_unreachable("Unexpected node");
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case ARMISD::CAND: Opc = ARM::ANDCCrr; break;
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case ARMISD::COR: Opc = ARM::ORRCCrr; break;
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case ARMISD::CXOR: Opc = ARM::EORCCrr; break;
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}
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SDValue Ops[] = { FalseVal, TrueVal, CC, CCR, Reg0, InFlag };
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return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 6);
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}
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/// Target-specific DAG combining for ISD::XOR.
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/// Target-independent combining lowers SELECT_CC nodes of the form
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/// select_cc setg[ge] X, 0, X, -X
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@ -2714,6 +2822,10 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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}
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case ARMISD::CMOV:
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return SelectCMOVOp(N);
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case ARMISD::CAND:
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case ARMISD::COR:
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case ARMISD::CXOR:
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return SelectConditionalOp(N);
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case ARMISD::VZIP: {
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unsigned Opc = 0;
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EVT VT = N->getValueType(0);
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@ -794,10 +794,11 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setTargetDAGCombine(ISD::SUB);
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setTargetDAGCombine(ISD::MUL);
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if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
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setTargetDAGCombine(ISD::OR);
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if (Subtarget->hasNEON())
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if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON()) {
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setTargetDAGCombine(ISD::AND);
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setTargetDAGCombine(ISD::OR);
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setTargetDAGCombine(ISD::XOR);
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}
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setStackPointerRegisterToSaveRestore(ARM::SP);
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@ -890,7 +891,11 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
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case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
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case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
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case ARMISD::CMOV: return "ARMISD::CMOV";
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case ARMISD::CAND: return "ARMISD::CAND";
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case ARMISD::COR: return "ARMISD::COR";
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case ARMISD::CXOR: return "ARMISD::CXOR";
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case ARMISD::RBIT: return "ARMISD::RBIT";
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@ -6843,8 +6848,52 @@ static SDValue PerformMULCombine(SDNode *N,
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return SDValue();
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}
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static bool isCMOVWithZeroOrAllOnesLHS(SDValue N, bool AllOnes) {
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if (N.getOpcode() != ARMISD::CMOV || !N.getNode()->hasOneUse())
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return false;
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SDValue FalseVal = N.getOperand(0);
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ConstantSDNode *C = dyn_cast<ConstantSDNode>(FalseVal);
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if (!C)
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return false;
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if (AllOnes)
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return C->isAllOnesValue();
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return C->isNullValue();
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}
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/// formConditionalOp - Combine an operation with a conditional move operand
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/// to form a conditional op. e.g. (or x, (cmov 0, y, cond)) => (or.cond x, y)
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/// (and x, (cmov -1, y, cond)) => (and.cond, x, y)
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static SDValue formConditionalOp(SDNode *N, SelectionDAG &DAG,
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bool Commutable) {
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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bool isAND = N->getOpcode() == ISD::AND;
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bool isCand = isCMOVWithZeroOrAllOnesLHS(N1, isAND);
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if (!isCand && Commutable) {
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isCand = isCMOVWithZeroOrAllOnesLHS(N0, isAND);
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if (isCand)
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std::swap(N0, N1);
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}
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if (!isCand)
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return SDValue();
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unsigned Opc = 0;
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switch (N->getOpcode()) {
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default: llvm_unreachable("Unexpected node");
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case ISD::AND: Opc = ARMISD::CAND; break;
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case ISD::OR: Opc = ARMISD::COR; break;
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case ISD::XOR: Opc = ARMISD::CXOR; break;
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}
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return DAG.getNode(Opc, N->getDebugLoc(), N->getValueType(0), N0,
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N1.getOperand(1), N1.getOperand(2), N1.getOperand(3),
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N1.getOperand(4));
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}
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static SDValue PerformANDCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI) {
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TargetLowering::DAGCombinerInfo &DCI,
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const ARMSubtarget *Subtarget) {
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// Attempt to use immediate-form VBIC
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BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
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@ -6875,6 +6924,13 @@ static SDValue PerformANDCombine(SDNode *N,
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}
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}
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if (!Subtarget->isThumb1Only()) {
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// (and x, (cmov -1, y, cond)) => (and.cond x, y)
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SDValue CAND = formConditionalOp(N, DAG, true);
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if (CAND.getNode())
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return CAND;
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}
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return SDValue();
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}
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@ -6911,6 +6967,13 @@ static SDValue PerformORCombine(SDNode *N,
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}
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}
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if (!Subtarget->isThumb1Only()) {
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// (or x, (cmov 0, y, cond)) => (or.cond x, y)
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SDValue COR = formConditionalOp(N, DAG, true);
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if (COR.getNode())
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return COR;
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}
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SDValue N0 = N->getOperand(0);
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if (N0.getOpcode() != ISD::AND)
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return SDValue();
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@ -7059,6 +7122,25 @@ static SDValue PerformORCombine(SDNode *N,
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return SDValue();
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}
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static SDValue PerformXORCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI,
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const ARMSubtarget *Subtarget) {
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EVT VT = N->getValueType(0);
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SelectionDAG &DAG = DCI.DAG;
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if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
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return SDValue();
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if (!Subtarget->isThumb1Only()) {
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// (xor x, (cmov 0, y, cond)) => (xor.cond x, y)
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SDValue CXOR = formConditionalOp(N, DAG, true);
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if (CXOR.getNode())
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return CXOR;
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}
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return SDValue();
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}
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/// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
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/// the bits being cleared by the AND are not demanded by the BFI.
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static SDValue PerformBFICombine(SDNode *N,
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@ -8110,7 +8192,8 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::SUB: return PerformSUBCombine(N, DCI);
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case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
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case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
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case ISD::AND: return PerformANDCombine(N, DCI);
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case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
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case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
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case ARMISD::BFI: return PerformBFICombine(N, DCI);
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case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
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case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
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@ -56,7 +56,11 @@ namespace llvm {
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CMPFP, // ARM VFP compare instruction, sets FPSCR.
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CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
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FMSTAT, // ARM fmstat instruction.
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CMOV, // ARM conditional move instructions.
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CAND, // ARM conditional and instructions.
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COR, // ARM conditional or instructions.
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CXOR, // ARM conditional xor instructions.
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BCC_i64,
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@ -4084,6 +4084,73 @@ def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
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4, IIC_iCMOVi,
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[/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
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RegConstraint<"$false = $Rd">;
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let isCodeGenOnly = 1 in {
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// Conditional instructions
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multiclass AsI1_bincc_irs<bits<4> opcod, string opc,
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InstrItinClass iii, InstrItinClass iir, InstrItinClass iis> {
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def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
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iii, opc, "\t$Rd, $Rn, $imm", []>,
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RegConstraint<"$Rn = $Rd"> {
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bits<4> Rd;
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bits<4> Rn;
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bits<12> imm;
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let Inst{25} = 1;
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let Inst{19-16} = Rn;
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let Inst{15-12} = Rd;
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let Inst{11-0} = imm;
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}
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def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
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iir, opc, "\t$Rd, $Rn, $Rm", []>,
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RegConstraint<"$Rn = $Rd"> {
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bits<4> Rd;
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bits<4> Rn;
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bits<4> Rm;
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let Inst{25} = 0;
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let Inst{19-16} = Rn;
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let Inst{15-12} = Rd;
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let Inst{11-4} = 0b00000000;
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let Inst{3-0} = Rm;
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}
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def rsi : AsI1<opcod, (outs GPR:$Rd),
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(ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
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iis, opc, "\t$Rd, $Rn, $shift", []>,
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RegConstraint<"$Rn = $Rd"> {
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bits<4> Rd;
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bits<4> Rn;
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bits<12> shift;
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let Inst{25} = 0;
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let Inst{19-16} = Rn;
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let Inst{15-12} = Rd;
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let Inst{11-5} = shift{11-5};
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let Inst{4} = 0;
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let Inst{3-0} = shift{3-0};
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}
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def rsr : AsI1<opcod, (outs GPR:$Rd),
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(ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
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iis, opc, "\t$Rd, $Rn, $shift", []>,
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RegConstraint<"$Rn = $Rd"> {
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bits<4> Rd;
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bits<4> Rn;
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bits<12> shift;
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let Inst{25} = 0;
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let Inst{19-16} = Rn;
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let Inst{15-12} = Rd;
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let Inst{11-8} = shift{11-8};
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let Inst{7} = 0;
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let Inst{6-5} = shift{6-5};
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let Inst{4} = 1;
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let Inst{3-0} = shift{3-0};
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}
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} // AsI1_bincc_irs
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defm ANDCC : AsI1_bincc_irs<0b0000, "and", IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
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defm ORRCC : AsI1_bincc_irs<0b1100, "orr", IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
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defm EORCC : AsI1_bincc_irs<0b0001, "eor", IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
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} // isCodeGenOnly
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} // neverHasSideEffects
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//===----------------------------------------------------------------------===//
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|
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@ -2943,6 +2943,44 @@ def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
|
||||
(ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
|
||||
IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
|
||||
RegConstraint<"$false = $Rd">;
|
||||
|
||||
multiclass T2I_bincc_irs<bits<4> opcod, string opc,
|
||||
InstrItinClass iii, InstrItinClass iir, InstrItinClass iis> {
|
||||
// shifted imm
|
||||
def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
|
||||
iii, opc, ".w\t$Rd, $Rn, $imm", []>,
|
||||
RegConstraint<"$Rn = $Rd"> {
|
||||
let Inst{31-27} = 0b11110;
|
||||
let Inst{25} = 0;
|
||||
let Inst{24-21} = opcod;
|
||||
let Inst{15} = 0;
|
||||
}
|
||||
// register
|
||||
def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
|
||||
iir, opc, ".w\t$Rd, $Rn, $Rm", []>,
|
||||
RegConstraint<"$Rn = $Rd"> {
|
||||
let Inst{31-27} = 0b11101;
|
||||
let Inst{26-25} = 0b01;
|
||||
let Inst{24-21} = opcod;
|
||||
let Inst{14-12} = 0b000; // imm3
|
||||
let Inst{7-6} = 0b00; // imm2
|
||||
let Inst{5-4} = 0b00; // type
|
||||
}
|
||||
// shifted register
|
||||
def rs : T2sTwoRegShiftedReg<(outs rGPR:$Rd),
|
||||
(ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
|
||||
iis, opc, ".w\t$Rd, $Rn, $ShiftedRm", []>,
|
||||
RegConstraint<"$Rn = $Rd"> {
|
||||
let Inst{31-27} = 0b11101;
|
||||
let Inst{26-25} = 0b01;
|
||||
let Inst{24-21} = opcod;
|
||||
}
|
||||
} // T2I_bincc_irs
|
||||
|
||||
defm t2ANDCC : T2I_bincc_irs<0b0000, "and", IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
|
||||
defm t2ORRCC : T2I_bincc_irs<0b0010, "orr", IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
|
||||
defm t2EORCC : T2I_bincc_irs<0b0100, "eor", IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
|
||||
|
||||
} // isCodeGenOnly = 1
|
||||
} // neverHasSideEffects
|
||||
|
||||
|
||||
@ -58,3 +58,49 @@ define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
|
||||
%s = or i32 %z, %y
|
||||
ret i32 %s
|
||||
}
|
||||
|
||||
define i32 @t5(i32 %a, i32 %b, i32 %c) nounwind {
|
||||
entry:
|
||||
; ARM: t5:
|
||||
; ARM-NOT: moveq
|
||||
; ARM: orreq r2, r2, #1
|
||||
|
||||
; T2: t5:
|
||||
; T2-NOT: moveq
|
||||
; T2: orreq.w r2, r2, #1
|
||||
%tmp1 = icmp eq i32 %a, %b
|
||||
%tmp2 = zext i1 %tmp1 to i32
|
||||
%tmp3 = or i32 %tmp2, %c
|
||||
ret i32 %tmp3
|
||||
}
|
||||
|
||||
define i32 @t6(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
|
||||
; ARM: t6:
|
||||
; ARM-NOT: movge
|
||||
; ARM: eorlt r3, r3, r2
|
||||
|
||||
; T2: t6:
|
||||
; T2-NOT: movge
|
||||
; T2: eorlt.w r3, r3, r2
|
||||
%cond = icmp slt i32 %a, %b
|
||||
%tmp1 = select i1 %cond, i32 %c, i32 0
|
||||
%tmp2 = xor i32 %tmp1, %d
|
||||
ret i32 %tmp2
|
||||
}
|
||||
|
||||
define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind {
|
||||
entry:
|
||||
; ARM: t7:
|
||||
; ARM-NOT: lsleq
|
||||
; ARM: andeq r2, r2, r2, lsl #1
|
||||
|
||||
; T2: t7:
|
||||
; T2-NOT: lsleq.w
|
||||
; T2: andeq.w r2, r2, r2, lsl #1
|
||||
%tmp1 = shl i32 %c, 1
|
||||
%cond = icmp eq i32 %a, %b
|
||||
%tmp2 = select i1 %cond, i32 %tmp1, i32 -1
|
||||
%tmp3 = and i32 %c, %tmp2
|
||||
ret i32 %tmp3
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user