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[AMDGPU] Expand vector mulhu/mulhs

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Differential revision: https://reviews.llvm.org/D26077

llvm-svn: 285684
This commit is contained in:
Valery Pykhtin 2016-11-01 10:26:48 +00:00
parent 87dcd90e97
commit d1c9440bfa
3 changed files with 28 additions and 0 deletions
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2
lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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@ -359,6 +359,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FP_TO_SINT, VT, Expand);
setOperationAction(ISD::FP_TO_UINT, VT, Expand);
setOperationAction(ISD::MUL, VT, Expand);
setOperationAction(ISD::MULHU, VT, Expand);
setOperationAction(ISD::MULHS, VT, Expand);
setOperationAction(ISD::OR, VT, Expand);
setOperationAction(ISD::SHL, VT, Expand);
setOperationAction(ISD::SRA, VT, Expand);

13
test/CodeGen/AMDGPU/sdiv.ll
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@ -156,3 +156,16 @@ define void @v_sdiv_i25(i32 addrspace(1)* %out, i25 addrspace(1)* %in) {
; store i64 %result, i64 addrspace(1)* %out, align 8
; ret void
; }
; FUNC-LABEL: @scalarize_mulhs_4xi32
; SI: v_mul_hi_i32
; SI: v_mul_hi_i32
; SI: v_mul_hi_i32
; SI: v_mul_hi_i32
define void @scalarize_mulhs_4xi32(<4 x i32> addrspace(1)* nocapture readonly %in, <4 x i32> addrspace(1)* nocapture %out) {
%1 = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16
%2 = sdiv <4 x i32> %1, <i32 53668, i32 53668, i32 53668, i32 53668>
store <4 x i32> %2, <4 x i32> addrspace(1)* %out, align 16
ret void
}

13
test/CodeGen/AMDGPU/udiv.ll
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@ -145,3 +145,16 @@ define void @v_udiv_i24(i32 addrspace(1)* %out, i24 addrspace(1)* %in) {
store i32 %result.ext, i32 addrspace(1)* %out
ret void
}
; FUNC-LABEL: @scalarize_mulhu_4xi32
; SI: v_mul_hi_u32
; SI: v_mul_hi_u32
; SI: v_mul_hi_u32
; SI: v_mul_hi_u32
define void @scalarize_mulhu_4xi32(<4 x i32> addrspace(1)* nocapture readonly %in, <4 x i32> addrspace(1)* nocapture %out) {
%1 = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16
%2 = udiv <4 x i32> %1, <i32 53668, i32 53668, i32 53668, i32 53668>
store <4 x i32> %2, <4 x i32> addrspace(1)* %out, align 16
ret void
}