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[mips] [IAS] Unify common functionality of LA and LI.
Summary: A side-effect of this is that LA gains proper handling of unsigned and positive signed 16-bit immediates and more accurate error messages. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9290 llvm-svn: 237255
This commit is contained in:
Toma Tabacu
parent
b27364c475
commit
d3389f5bbb
@ -179,13 +179,17 @@ class MipsAsmParser : public MCTargetAsmParser {
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bool expandJalWithRegs(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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bool loadImmediate(int64_t ImmValue, unsigned DstReg, unsigned SrcReg,
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bool Is32BitImm, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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bool expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
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bool expandLoadAddressImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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bool expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
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bool expandLoadAddressReg(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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@ -203,6 +207,9 @@ class MipsAsmParser : public MCTargetAsmParser {
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void createNop(bool hasShortDelaySlot, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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void createAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg,
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SmallVectorImpl<MCInst> &Instructions);
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bool reportParseError(Twine ErrorMsg);
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bool reportParseError(SMLoc Loc, Twine ErrorMsg);
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@ -1615,9 +1622,9 @@ bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
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case Mips::LoadImm64:
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return expandLoadImm(Inst, false, IDLoc, Instructions);
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case Mips::LoadAddrImm32:
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return expandLoadAddressImm(Inst, IDLoc, Instructions);
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return expandLoadAddressImm(Inst, true, IDLoc, Instructions);
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case Mips::LoadAddrReg32:
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return expandLoadAddressReg(Inst, IDLoc, Instructions);
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return expandLoadAddressReg(Inst, true, IDLoc, Instructions);
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case Mips::B_MM_Pseudo:
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return expandUncondBranchMMPseudo(Inst, IDLoc, Instructions);
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case Mips::SWM_MM:
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@ -1713,21 +1720,20 @@ bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc,
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return false;
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}
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bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
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bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
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unsigned SrcReg, bool Is32BitImm, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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if (!Is32BitImm && !isGP64bit()) {
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Error(IDLoc, "instruction requires a 64-bit architecture");
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return true;
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}
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MCInst tmpInst;
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const MCOperand &ImmOp = Inst.getOperand(1);
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assert(ImmOp.isImm() && "expected immediate operand kind");
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const MCOperand &RegOp = Inst.getOperand(0);
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assert(RegOp.isReg() && "expected register operand kind");
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bool UseSrcReg = false;
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if (SrcReg != Mips::NoRegister)
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UseSrcReg = true;
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MCInst tmpInst;
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int64_t ImmValue = ImmOp.getImm();
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unsigned Reg = RegOp.getReg();
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tmpInst.setLoc(IDLoc);
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// FIXME: gas has a special case for values that are 000...1111, which
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// becomes a li -1 and then a dsrl
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@ -1735,16 +1741,17 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
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// For unsigned and positive signed 16-bit values (0 <= j <= 65535):
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// li d,j => ori d,$zero,j
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tmpInst.setOpcode(Mips::ORi);
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tmpInst.addOperand(MCOperand::CreateReg(Reg));
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tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
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tmpInst.addOperand(MCOperand::CreateReg(DstReg));
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tmpInst.addOperand(MCOperand::CreateReg(
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UseSrcReg ? SrcReg : (isGP64bit() ? Mips::ZERO_64 : Mips::ZERO)));
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tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
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Instructions.push_back(tmpInst);
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} else if (ImmValue < 0 && ImmValue >= -32768) {
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// For negative signed 16-bit values (-32768 <= j < 0):
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// li d,j => addiu d,$zero,j
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tmpInst.setOpcode(Mips::ADDiu);
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tmpInst.addOperand(MCOperand::CreateReg(Reg));
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tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
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tmpInst.addOperand(MCOperand::CreateReg(DstReg));
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tmpInst.addOperand(MCOperand::CreateReg(UseSrcReg ? SrcReg : Mips::ZERO));
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tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
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Instructions.push_back(tmpInst);
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} else if ((ImmValue & 0xffffffff) == ImmValue) {
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@ -1755,10 +1762,14 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
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uint16_t Bits15To0 = ImmValue & 0xffff;
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tmpInst.setOpcode(Mips::LUi);
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tmpInst.addOperand(MCOperand::CreateReg(Reg));
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tmpInst.addOperand(MCOperand::CreateReg(DstReg));
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tmpInst.addOperand(MCOperand::CreateImm(Bits31To16));
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Instructions.push_back(tmpInst);
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createLShiftOri<0>(Bits15To0, Reg, IDLoc, Instructions);
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createLShiftOri<0>(Bits15To0, DstReg, IDLoc, Instructions);
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if (UseSrcReg)
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createAddu(DstReg, DstReg, SrcReg, Instructions);
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} else if ((ImmValue & (0xffffLL << 48)) == 0) {
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if (Is32BitImm) {
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Error(IDLoc, "instruction requires a 32-bit immediate");
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@ -1783,11 +1794,15 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
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uint16_t Bits15To0 = ImmValue & 0xffff;
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tmpInst.setOpcode(Mips::LUi);
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tmpInst.addOperand(MCOperand::CreateReg(Reg));
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tmpInst.addOperand(MCOperand::CreateReg(DstReg));
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tmpInst.addOperand(MCOperand::CreateImm(Bits47To32));
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Instructions.push_back(tmpInst);
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createLShiftOri<0>(Bits31To16, Reg, IDLoc, Instructions);
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createLShiftOri<16>(Bits15To0, Reg, IDLoc, Instructions);
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createLShiftOri<0>(Bits31To16, DstReg, IDLoc, Instructions);
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createLShiftOri<16>(Bits15To0, DstReg, IDLoc, Instructions);
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if (UseSrcReg)
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createAddu(DstReg, DstReg, SrcReg, Instructions);
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} else {
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if (Is32BitImm) {
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Error(IDLoc, "instruction requires a 32-bit immediate");
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@ -1814,27 +1829,43 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
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uint16_t Bits15To0 = ImmValue & 0xffff;
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tmpInst.setOpcode(Mips::LUi);
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tmpInst.addOperand(MCOperand::CreateReg(Reg));
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tmpInst.addOperand(MCOperand::CreateReg(DstReg));
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tmpInst.addOperand(MCOperand::CreateImm(Bits63To48));
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Instructions.push_back(tmpInst);
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createLShiftOri<0>(Bits47To32, Reg, IDLoc, Instructions);
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createLShiftOri<0>(Bits47To32, DstReg, IDLoc, Instructions);
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// When Bits31To16 is 0, do a left shift of 32 bits instead of doing
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// two left shifts of 16 bits.
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if (Bits31To16 == 0) {
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createLShiftOri<32>(Bits15To0, Reg, IDLoc, Instructions);
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createLShiftOri<32>(Bits15To0, DstReg, IDLoc, Instructions);
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} else {
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createLShiftOri<16>(Bits31To16, Reg, IDLoc, Instructions);
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createLShiftOri<16>(Bits15To0, Reg, IDLoc, Instructions);
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createLShiftOri<16>(Bits31To16, DstReg, IDLoc, Instructions);
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createLShiftOri<16>(Bits15To0, DstReg, IDLoc, Instructions);
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}
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if (UseSrcReg)
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createAddu(DstReg, DstReg, SrcReg, Instructions);
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}
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return false;
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}
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bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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const MCOperand &ImmOp = Inst.getOperand(1);
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assert(ImmOp.isImm() && "expected immediate operand kind");
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const MCOperand &DstRegOp = Inst.getOperand(0);
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assert(DstRegOp.isReg() && "expected register operand kind");
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if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
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Is32BitImm, IDLoc, Instructions))
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return true;
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return false;
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}
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bool
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MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
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MipsAsmParser::expandLoadAddressReg(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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MCInst tmpInst;
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const MCOperand &ImmOp = Inst.getOperand(2);
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assert((ImmOp.isImm() || ImmOp.isExpr()) &&
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"expected immediate operand kind");
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@ -1846,44 +1877,17 @@ MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
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assert(SrcRegOp.isReg() && "expected register operand kind");
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const MCOperand &DstRegOp = Inst.getOperand(0);
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assert(DstRegOp.isReg() && "expected register operand kind");
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int ImmValue = ImmOp.getImm();
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if (-32768 <= ImmValue && ImmValue <= 65535) {
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// For -32768 <= j <= 65535.
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// la d,j(s) => addiu d,s,j
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tmpInst.setOpcode(Mips::ADDiu);
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tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
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tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
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tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
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Instructions.push_back(tmpInst);
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} else {
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// For any other value of j that is representable as a 32-bit integer.
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// la d,j(s) => lui d,hi16(j)
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// ori d,d,lo16(j)
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// addu d,d,s
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tmpInst.setOpcode(Mips::LUi);
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tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
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tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
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Instructions.push_back(tmpInst);
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tmpInst.clear();
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tmpInst.setOpcode(Mips::ORi);
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tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
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tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
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tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
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Instructions.push_back(tmpInst);
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tmpInst.clear();
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tmpInst.setOpcode(Mips::ADDu);
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tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
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tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
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tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
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Instructions.push_back(tmpInst);
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}
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if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), SrcRegOp.getReg(),
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Is32BitImm, IDLoc, Instructions))
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return true;
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return false;
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}
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bool
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MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
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MipsAsmParser::expandLoadAddressImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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MCInst tmpInst;
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const MCOperand &ImmOp = Inst.getOperand(1);
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assert((ImmOp.isImm() || ImmOp.isExpr()) &&
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"expected immediate operand kind");
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@ -1891,32 +1895,13 @@ MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
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expandLoadAddressSym(Inst, IDLoc, Instructions);
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return false;
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}
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const MCOperand &RegOp = Inst.getOperand(0);
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assert(RegOp.isReg() && "expected register operand kind");
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int ImmValue = ImmOp.getImm();
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if (-32768 <= ImmValue && ImmValue <= 65535) {
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// For -32768 <= j <= 65535.
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// la d,j => addiu d,$zero,j
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tmpInst.setOpcode(Mips::ADDiu);
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tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
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tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
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tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
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Instructions.push_back(tmpInst);
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} else {
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// For any other value of j that is representable as a 32-bit integer.
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// la d,j => lui d,hi16(j)
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// ori d,d,lo16(j)
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tmpInst.setOpcode(Mips::LUi);
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tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
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tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
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Instructions.push_back(tmpInst);
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tmpInst.clear();
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tmpInst.setOpcode(Mips::ORi);
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tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
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tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
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tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
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Instructions.push_back(tmpInst);
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}
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const MCOperand &DstRegOp = Inst.getOperand(0);
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assert(DstRegOp.isReg() && "expected register operand kind");
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if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
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Is32BitImm, IDLoc, Instructions))
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return true;
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return false;
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}
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@ -2179,6 +2164,17 @@ void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
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Instructions.push_back(NopInst);
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}
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void MipsAsmParser::createAddu(unsigned DstReg, unsigned SrcReg,
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unsigned TrgReg,
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SmallVectorImpl<MCInst> &Instructions) {
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MCInst AdduInst;
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AdduInst.setOpcode(Mips::ADDu);
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AdduInst.addOperand(MCOperand::CreateReg(DstReg));
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AdduInst.addOperand(MCOperand::CreateReg(SrcReg));
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AdduInst.addOperand(MCOperand::CreateReg(TrgReg));
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Instructions.push_back(AdduInst);
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}
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unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
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// As described by the Mips32r2 spec, the registers Rd and Rs for
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// jalr.hb must be different.
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@ -9,10 +9,10 @@
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# CHECK: addiu $6, $zero, -2345 # encoding: [0xc0,0x30,0xd7,0xf6]
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# CHECK: lui $7, 1 # encoding: [0xa7,0x41,0x01,0x00]
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# CHECK: ori $7, $7, 2 # encoding: [0xe7,0x50,0x02,0x00]
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# CHECK: addiu $4, $zero, 20 # encoding: [0x80,0x30,0x14,0x00]
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# CHECK: ori $4, $zero, 20 # encoding: [0x80,0x50,0x14,0x00]
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# CHECK: lui $7, 1 # encoding: [0xa7,0x41,0x01,0x00]
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# CHECK: ori $7, $7, 2 # encoding: [0xe7,0x50,0x02,0x00]
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# CHECK: addiu $4, $5, 20 # encoding: [0x85,0x30,0x14,0x00]
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# CHECK: ori $4, $5, 20 # encoding: [0x85,0x50,0x14,0x00]
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# CHECK: lui $7, 1 # encoding: [0xa7,0x41,0x01,0x00]
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# CHECK: ori $7, $7, 2 # encoding: [0xe7,0x50,0x02,0x00]
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# CHECK: addu $7, $7, $8 # encoding: [0x07,0x01,0x50,0x39]
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@ -7,5 +7,11 @@
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li $5, 0x100000000
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# 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
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# 64-BIT: :[[@LINE-2]]:3: error: instruction requires a 32-bit immediate
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la $5, 0x100000000
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# 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
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# 64-BIT: :[[@LINE-2]]:3: error: instruction requires a 32-bit immediate
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la $5, 0x100000000($6)
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# 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
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# 64-BIT: :[[@LINE-2]]:3: error: instruction requires a 32-bit immediate
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dli $5, 1
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# 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture
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@ -12,10 +12,10 @@
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# CHECK: lui $9, 1 # encoding: [0x01,0x00,0x09,0x3c]
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# CHECK-NOT: ori $9, $9, 0 # encoding: [0x00,0x00,0x29,0x35]
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# CHECK: addiu $4, $zero, 20 # encoding: [0x14,0x00,0x04,0x24]
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# CHECK: ori $4, $zero, 20 # encoding: [0x14,0x00,0x04,0x34]
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# CHECK: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c]
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# CHECK: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34]
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# CHECK: addiu $4, $5, 20 # encoding: [0x14,0x00,0xa4,0x24]
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# CHECK: ori $4, $5, 20 # encoding: [0x14,0x00,0xa4,0x34]
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# CHECK: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c]
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# CHECK: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34]
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# CHECK: addu $7, $7, $8 # encoding: [0x21,0x38,0xe8,0x00]
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