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Fix a tblgen subtargetemitter bug, for future Swift support.
This fixes some of the ridiculously complex code for optimizing the machine model tables that are shared among all processors of a given target. A9 and Swift both use the "special" feature that maps old itinerary classes to new machine model defs. They map different overlapping subsets of instructions, which wasn't handled correctly. llvm-svn: 183302
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@ -710,16 +710,35 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) {
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ArrayRef<Record*> InstDefs = ClassInstrs[CIdx].second;
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// If the all instrs in the current class are accounted for, then leave
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// them mapped to their old class.
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if (OldSCIdx && SchedClasses[OldSCIdx].InstRWs.size() == InstDefs.size()) {
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assert(SchedClasses[OldSCIdx].ProcIndices[0] == 0 &&
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"expected a generic SchedClass");
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continue;
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if (OldSCIdx) {
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const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs;
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if (!RWDefs.empty()) {
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const RecVec *OrigInstDefs = Sets.expand(RWDefs[0]);
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unsigned OrigNumInstrs = 0;
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for (RecIter I = OrigInstDefs->begin(), E = OrigInstDefs->end();
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I != E; ++I) {
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if (InstrClassMap[*I] == OldSCIdx)
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++OrigNumInstrs;
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}
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if (OrigNumInstrs == InstDefs.size()) {
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assert(SchedClasses[OldSCIdx].ProcIndices[0] == 0 &&
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"expected a generic SchedClass");
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DEBUG(dbgs() << "InstRW: Reuse SC " << OldSCIdx << ":"
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<< SchedClasses[OldSCIdx].Name << " on "
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<< InstRWDef->getValueAsDef("SchedModel")->getName() << "\n");
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SchedClasses[OldSCIdx].InstRWs.push_back(InstRWDef);
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continue;
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}
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}
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}
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unsigned SCIdx = SchedClasses.size();
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SchedClasses.resize(SCIdx+1);
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CodeGenSchedClass &SC = SchedClasses.back();
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SC.Index = SCIdx;
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SC.Name = createSchedClassName(InstDefs);
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DEBUG(dbgs() << "InstRW: New SC " << SCIdx << ":" << SC.Name << " on "
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<< InstRWDef->getValueAsDef("SchedModel")->getName() << "\n");
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// Preserve ItinDef and Writes/Reads for processors without an InstRW entry.
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SC.ItinClassDef = SchedClasses[OldSCIdx].ItinClassDef;
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SC.Writes = SchedClasses[OldSCIdx].Writes;
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