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AMDGPU: Don't use separate mulhu/mulhs Pats

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llvm-svn: 258515
This commit is contained in:
Matt Arsenault 2016-01-22 18:42:49 +00:00
parent 351925633e
commit d4ad2318d1
1 changed files with 2 additions and 12 deletions
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14
lib/Target/AMDGPU/SIInstructions.td
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@ -1754,14 +1754,14 @@ defm V_MUL_LO_U32 : VOP3Inst <vop3<0x169, 0x285>, "v_mul_lo_u32",
VOP_I32_I32_I32
>;
defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a, 0x286>, "v_mul_hi_u32",
VOP_I32_I32_I32
VOP_I32_I32_I32, mulhu
>;
defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b, 0x285>, "v_mul_lo_i32",
VOP_I32_I32_I32
>;
defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32",
VOP_I32_I32_I32
VOP_I32_I32_I32, mulhs
>;
} // isCommutable = 1, SchedRW = [WriteQuarterRate32]
@ -2772,16 +2772,6 @@ def : Pat <
def : IMad24Pat<V_MAD_I32_I24>;
def : UMad24Pat<V_MAD_U32_U24>;
def : Pat <
(mulhu i32:$src0, i32:$src1),
(V_MUL_HI_U32 $src0, $src1)
>;
def : Pat <
(mulhs i32:$src0, i32:$src1),
(V_MUL_HI_I32 $src0, $src1)
>;
defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>;
def : ROTRPattern <V_ALIGNBIT_B32>;